公开(公告)号：US12069848B2

公开(公告)日：2024-08-20

申请号：US17729450

申请日：2022-04-26

Applicant: Micron Technology, Inc.

Inventor： Kuo-Chen Wang ,  Terrence B. McDaniel ,  Russell A. Benson ,  Vinay Nair

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/485 ,  H10B12/50

Abstract: Methods, apparatuses, and systems related to a sense line and cell contact for a semiconductor structure are described. An example apparatus includes a first source/drain region and a second source/drain region, where the first source/drain region and the second source/drain region are separated by a channel, a gate opposing the channel, a sense line material coupled to the first source/drain region by a cell contact, where the cell contact is made from a combination of a first polysilicon material and a second polysilicon material, and a storage node coupled to the second source/drain region.

公开(公告)号：US20240040775A1

公开(公告)日：2024-02-01

申请号：US18478031

申请日：2023-09-29

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Kunal R. Parekh ,  Terrence B. McDaniel ,  Beau D. Barry

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/50 ,  H10B12/315 ,  H10B12/0335 ,  H10B12/482 ,  H10B12/488

Abstract: A method of forming a microelectronic device comprises forming a first microelectronic device structure comprising a first semiconductor structure, a first isolation material over the first semiconductor structure, and first conductive routing structures over the first semiconductor structure and surrounded by the first isolation material. A second microelectronic device structure comprising a second semiconductor structure and a second isolation material over the second semiconductor structure is formed. The second isolation material is bonded to the first isolation material to attach the second microelectronic device structure to the first microelectronic device structure. Memory cells comprising portions of the second semiconductor structure are formed after attaching the second microelectronic device structure to the first microelectronic device structure. Control logic devices including transistors comprising portions of the first semiconductor structure are formed after forming the memory cells. Microelectronic devices, electronic systems, and additional methods are also described.

公开(公告)号：US11785764B2

公开(公告)日：2023-10-10

申请号：US17364281

申请日：2021-06-30

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Kunal R. Parekh ,  Terrence B. McDaniel ,  Beau D. Barry

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/0335 ,  H10B12/315 ,  H10B12/482 ,  H10B12/488 ,  H10B12/50

Abstract: A method of forming a microelectronic device comprises forming a first microelectronic device structure comprising a first semiconductor structure, a first isolation material over the first semiconductor structure, and first conductive routing structures over the first semiconductor structure and surrounded by the first isolation material. A second microelectronic device structure comprising a second semiconductor structure and a second isolation material over the second semiconductor structure is formed. The second isolation material is bonded to the first isolation material to attach the second microelectronic device structure to the first microelectronic device structure. Memory cells comprising portions of the second semiconductor structure are formed after attaching the second microelectronic device structure to the first microelectronic device structure. Control logic devices including transistors comprising portions of the first semiconductor structure are formed after forming the memory cells. Microelectronic devices, electronic systems, and additional methods are also described.

公开(公告)号：US20220358971A1

公开(公告)日：2022-11-10

申请号：US17669189

申请日：2022-02-10

Applicant: Micron Technology, Inc.

Inventor： Che-Chi Lee ,  Terrence B. McDaniel ,  Kehao Zhang ,  Albert P. Chan ,  Clement Jacob ,  Luca Fumagalli ,  Vinay Nair

IPC: G11C5/10 ,  H01L27/108 ,  H01L49/02 ,  G11C11/405 ,  H01L27/06

Abstract: Some embodiments include an integrated assembly having first and second source/drain regions laterally offset from one another. Metal silicide is adjacent to lateral surfaces of the source/drain regions. Metal is adjacent to the metal silicide. Container-shaped first and second capacitor electrodes are coupled to the source/drain regions through the metal silicide and the metal. Capacitor dielectric material lines interior surfaces of the container-shaped first and second capacitor electrodes, A shared capacitor electrode extends vertically between the first and second capacitor electrodes, and extends into the lined first and second capacitor electrodes. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11309315B2

公开(公告)日：2022-04-19

申请号：US16943108

申请日：2020-07-30

Applicant: Micron Technology, Inc.

Inventor： Terrence B. McDaniel ,  Si-Woo Lee ,  Vinay Nair ,  Luca Fumagalli

IPC: H01L27/108 ,  G11C5/06

Abstract: Systems, methods, and apparatuses are provided for digit line formation for horizontally oriented access devices. One example method includes forming layers of a first dielectric material, a low doped semiconductor material, and a second dielectric material, in repeating iterations vertically to form a vertical stack, forming a vertical opening in the vertical stack, selectively etching the second dielectric material to form a horizontal opening in the second dielectric material, gas phase doping a dopant on a top surface of the low doped semiconductor material in the horizontal opening to form a source/drain region, forming a high doped semiconductor material in the horizontal opening, selectively etching the high doped semiconductor material formed in the horizontal opening such that a portion of the high doped semiconductor material remains, and converting the remaining high doped semiconductor material to a conductive material having a different characteristic from the remaining high doped semiconductor material.

公开(公告)号：US20220037334A1

公开(公告)日：2022-02-03

申请号：US16943108

申请日：2020-07-30

Applicant: Micron Technology, Inc.

Inventor： Terrence B. McDaniel ,  Si-Woo Lee ,  Vinay Nair ,  Luca Fumagalli

IPC: H01L27/108 ,  G11C5/06

Abstract: Systems, methods, and apparatuses are provided for digit line formation for horizontally oriented access devices. One example method includes forming layers of a first dielectric material, a low doped semiconductor material, and a second dielectric material, in repeating iterations vertically to form a vertical stack, forming a vertical opening in the vertical stack, selectively etching the second dielectric material to form a horizontal opening in the second dielectric material, gas phase doping a dopant on a top surface of the low doped semiconductor material in the horizontal opening to form a source/drain region, forming a high doped semiconductor material in the horizontal opening, selectively etching the high doped semiconductor material formed in the horizontal opening such that a portion of the high doped semiconductor material remains, and converting the remaining high doped semiconductor material to a conductive material having a different characteristic from the remaining high doped semiconductor material.

公开(公告)号：US20240153541A1

公开(公告)日：2024-05-09

申请号：US18413671

申请日：2024-01-16

Applicant: Micron Technology, Inc.

Inventor： Che-Chi Lee ,  Terrence B. McDaniel ,  Kehao Zhang ,  Albert P. Chan ,  Clement Jacob ,  Luca Fumagalli ,  Vinay Nair

IPC: G11C5/10 ,  G11C11/405 ,  H01L27/06 ,  H10B12/00

CPC classification number: G11C5/10 ,  G11C11/405 ,  H01L27/0688 ,  H01L28/60 ,  H10B12/30

Abstract: Some embodiments include an integrated assembly having first and second source/drain regions laterally offset from one another. Metal silicide is adjacent to lateral surfaces of the source/drain regions. Metal is adjacent to the metal silicide. Container-shaped first and second capacitor electrodes are coupled to the source/drain regions through the metal silicide and the metal. Capacitor dielectric material lines interior surfaces of the container-shaped first and second capacitor electrodes, A shared capacitor electrode extends vertically between the first and second capacitor electrodes, and extends into the lined first and second capacitor electrodes. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20240071968A1

公开(公告)日：2024-02-29

申请号：US18199741

申请日：2023-05-19

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Terrence B. McDaniel ,  Wei Zhou

IPC: H01L23/00

CPC classification number: H01L24/08 ,  H01L24/05 ,  H01L24/80 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/0807 ,  H01L2224/08123 ,  H01L2224/08145 ,  H01L2224/80365 ,  H01L2224/80379 ,  H01L2224/80896 ,  H01L2924/04642 ,  H01L2924/0504 ,  H01L2924/0554 ,  H01L2924/059

Abstract: This document discloses techniques, apparatuses, and systems for semiconductor device interconnects formed through volumetric expansion. A semiconductor assembly is described that includes two semiconductor dies. The first semiconductor die and the second semiconductor die are bonded at a dielectric layer of the first semiconductor die and a dielectric layer of the second semiconductor die to create one or more interconnect openings. The first semiconductor die includes a reservoir of conductive material located adjacent to the one or more interconnect openings and having a width greater than a width of the one or more interconnect openings. The reservoir of conductive material is heated to volumetrically expand the reservoir of conductive material through the one or more interconnect openings to form one or more interconnects electrically coupling the first semiconductor die and the second semiconductor die. In this way, a connected semiconductor device may be assembled.

公开(公告)号：US11915777B2

公开(公告)日：2024-02-27

申请号：US17669189

申请日：2022-02-10

Applicant: Micron Technology, Inc.

Inventor： Che-Chi Lee ,  Terrence B. McDaniel ,  Kehao Zhang ,  Albert P. Chan ,  Clement Jacob ,  Luca Fumagalli ,  Vinay Nair

IPC: G11C11/24 ,  G11C5/10 ,  H01L49/02 ,  G11C11/405 ,  H01L27/06 ,  H10B12/00

CPC classification number: G11C5/10 ,  G11C11/405 ,  H01L27/0688 ,  H01L28/60 ,  H10B12/30

Abstract: Some embodiments include an integrated assembly having first and second source/drain regions laterally offset from one another. Metal silicide is adjacent to lateral surfaces of the source/drain regions. Metal is adjacent to the metal silicide. Container-shaped first and second capacitor electrodes are coupled to the source/drain regions through the metal silicide and the metal. Capacitor dielectric material lines interior surfaces of the container-shaped first and second capacitor electrodes, A shared capacitor electrode extends vertically between the first and second capacitor electrodes, and extends into the lined first and second capacitor electrodes. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20240063068A1

公开(公告)日：2024-02-22

申请号：US17892036

申请日：2022-08-19

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh ,  Bret K. Street ,  Terrence B. McDaniel ,  Jaekyu Song

IPC: H01L23/13 ,  H01L25/065 ,  H01L25/00 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L23/13 ,  H01L25/0652 ,  H01L25/50 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/5382 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/73

Abstract: A semiconductor device assembly comprises a package substrate including (i) an upper surface having a plurality of internal contacts, (ii) a lower surface having a plurality of external contacts coupled to the plurality of internal contacts, and (iii) a cavity extending into the package substrate. The assembly further comprises a stack of first semiconductor devices disposed in the cavity, an uppermost first semiconductor device of the stack having a plurality of stack contacts, and an interposer including (i) a bottom surface having a first plurality of lower contacts coupled to the plurality of stack contacts and a second plurality of lower contacts coupled to the plurality of internal contacts, and (ii) a top surface having a plurality of upper contacts coupled to the first and second pluralities of lower contacts. The assembly further comprises a second semiconductor device including a plurality of die contacts coupled to the plurality of upper contacts.