公开(公告)号：US11961801B2

公开(公告)日：2024-04-16

申请号：US17373121

申请日：2021-07-12

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Indra V. Chary ,  David H. Wells ,  Harsh Narendrakumar Jain ,  Umberto Maria Meotto ,  Paolo Tessariol

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

Abstract: Integrated circuitry comprises two three-dimensional (3D) array regions individually comprising tiers of electronic components. A stair-step region is between the two 3D-array regions. First stair-step structures alternate with second stair-step structures along a first direction within the stair-step region. The first stair-step structures individually comprise two opposing first flights of stairs in a first vertical cross-section along the first direction. The stairs in the first flights each have multiple different-depth treads in a second vertical cross-section that is along a second direction that is orthogonal to the first direction. The second stair-step structures individually comprise two opposing second flights of stairs in the first vertical cross-section. The stairs in the second flights each have only a single one tread along the second direction. Other embodiments, including method, are disclosed.

公开(公告)号：US20240029794A1

公开(公告)日：2024-01-25

申请号：US17868118

申请日：2022-07-19

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Anna Maria Conti ,  Harsh Narendrakumar Jain ,  H. Montgomery Manning

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11582

CPC classification number: G11C16/0483 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11582

Abstract: A method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack extends from a memory-array region into a stair-step region. The first tiers are conductive and the second tiers are insulative at least in a finished-circuitry construction. A first layer of imageable resist is exposed to actinic radiation and developed to form a first opening there-through in the stair-step region. The developed first layer is used in a plurality of alternating etching and lateral-trimming steps that widens the first opening and forms two opposing flights of stairs in the stack in the stair-step region. A second layer of imageable resist is formed directly above the two opposing flights of stairs. The second layer is exposed to actinic radiation and developed to form a second opening there-through. The second opening exposes all of the stairs of one of the two opposing flights. The second layer is directly above all of the stairs in the other of the two opposing flights. The developed second layer is used in a plurality of alternating etching and lateral-trimming steps that widens the second opening, lengthens at least one of the two opposing flights of stairs, and extends the two opposing flights of stairs deeper into the stack. Other embodiments, including structure, are disclosed.

公开(公告)号：US20240021521A1

公开(公告)日：2024-01-18

申请号：US17812616

申请日：2022-07-14

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Martin Jared Barclay ,  Harsh Narendrakumar Jain ,  Yiping Wang

IPC: H01L23/535 ,  G11C16/08 ,  H01L27/11529 ,  H01L27/11573

CPC classification number: H01L23/535 ,  G11C16/08 ,  H01L27/11529 ,  H01L27/11573

Abstract: Methods, systems, and devices for staircase structures for accessing three-dimensional (3D) memory arrays are described. A memory system may include an access region (e.g., a staircase region) that includes circuitry for accessing memory cells at respective levels of memory cells. The access region may include a channel through which a conductive pillar may couple a word line at a level of memory cells with decoder circuitry. During manufacture of the memory system, a channel material may be formed in the channel and etched to form a corner portion in the channel. During a partitioning of the channel, a nitride material over the corner portion may be etched and some of the corner portion may remain in the channel, which may prevent formation of a trench that may cause the conductive pillar to be uncoupled from the word line.

公开(公告)号：US11830815B2

公开(公告)日：2023-11-28

申请号：US17006600

申请日：2020-08-28

Applicant: Micron Technology, Inc.

Inventor： Harsh Narendrakumar Jain

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/53295 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: A microelectronic device comprises a first deck structure comprising alternating conductive structures and insulating structures arranged in tiers, each of the tiers individually comprising one of the conductive structures and one of the insulating structures, a second deck structure vertically overlying the first deck structure and comprising additional tiers of the conductive structures and insulative structures, a staircase structure within the first deck structure and having steps comprising edges of the tiers, a dielectric material covering the steps of the staircase structure and extending through the first deck structure, and a liner material interposed between the steps of the staircase structure and terminating at an interdeck region between the first deck structure and the second deck structure. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US11581264B2

公开(公告)日：2023-02-14

申请号：US16546759

申请日：2019-08-21

Applicant: Micron Technology, Inc.

Inventor： Rohit Kothari ,  Harsh Narendrakumar Jain ,  John D. Hopkins ,  Xiaosong Zhang

IPC: H01L23/544

Abstract: An electronic device comprising at least one high aspect ratio feature in a base stack of materials, overlay marks in or on only an upper portion of the base stack of materials, and an additional stack of materials adjacent the base stack of materials, the additional stack of materials comprising the at least one high aspect ratio feature. Additional electronic devices and memory devices are disclosed, as are methods of forming high aspect ratio features in an electronic device.

公开(公告)号：US20210257385A1

公开(公告)日：2021-08-19

申请号：US17215308

申请日：2021-03-29

Applicant: Micron Technology, Inc.

Inventor： Yi Hu ,  Merri L. Carlson ,  Anilkumar Chandolu ,  Indra V. Chary ,  David Daycock ,  Harsh Narendrakumar Jain ,  Matthew J. King ,  Jian Li ,  Brett D. Lowe ,  Prakash Rau Mokhna Rau ,  Lifang Xu

IPC: H01L27/11582 ,  H01L21/311 ,  H01L21/02 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11573 ,  H01L21/3213 ,  H01L27/11556

Abstract: A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. The TAV region comprises spaced operative TAV areas. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region laterally outside of and not within the operative TAV areas. Operative TAVs are formed in individual of the spaced operative TAV areas in the TAV region. Other methods and structure independent of method are disclosed.

公开(公告)号：US20210125920A1

公开(公告)日：2021-04-29

申请号：US16664618

申请日：2019-10-25

Applicant: Micron Technology, Inc.

Inventor： Yi Hu ,  Harsh Narendrakumar Jain ,  Matthew J. King

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions has a higher top than in the second regions. The seam tops in the second regions are elevationally-coincident with or below a bottom of an uppermost of the conductive tiers. Methods are disclosed.

公开(公告)号：US20210057349A1

公开(公告)日：2021-02-25

申请号：US16546759

申请日：2019-08-21

Applicant: Micron Technology, Inc.

Inventor： Rohit Kothari ,  Harsh Narendrakumar Jain ,  John D. Hopkins ,  Xiaosong Zhang

IPC: H01L23/544

Abstract: An electronic device comprising at least one high aspect ratio feature in a base stack of materials, overlay marks in or on only an upper portion of the base stack of materials, and an additional stack of materials adjacent the base stack of materials, the additional stack of materials comprising the at least one high aspect ratio feature. Additional electronic devices and memory devices are disclosed, as are methods of forming high aspect ratio features in an electronic device.

公开(公告)号：US20240258233A1

公开(公告)日：2024-08-01

申请号：US18420538

申请日：2024-01-23

Applicant: Micron Technology, Inc.

Inventor： Yiping Wang ,  Harsh Narendrakumar Jain

IPC: H01L23/528 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/31111 ,  H01L21/76877 ,  H01L29/4011

Abstract: Methods, systems, and devices for staircase landing pads via rivets are described. A memory device may include a staircase region with a stack of materials that includes a set of word lines, where the set of word lines progressively decrease in length to form a staircase structure. The staircase region may additionally include a rivet that couples a first word line from the set of word lines with a conductive pillar. Additionally, the conductive pillar may traverse the stack perpendicularly to the set of word lines and may couple the first word line with supporting circuitry. In some cases, a first thickness of the first word line adjacent to the conductive pillar may be greater than a second thickness of other word lines adjacent to the conductive pillar. The staircase region may additionally include an oxide material that isolates the conductive pillar from the other word lines.

公开(公告)号：US20240196606A1

公开(公告)日：2024-06-13

申请号：US18513430

申请日：2023-11-17

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Harsh Narendrakumar Jain ,  Indra V. Chary ,  Richard J. Hill

IPC: H10B41/35 ,  G11C5/02 ,  G11C16/04 ,  H10B41/10 ,  H10B41/20 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35

CPC classification number: H10B41/35 ,  G11C5/025 ,  G11C16/0483 ,  H10B41/10 ,  H10B41/20 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35

Abstract: A microelectronic device includes a stack structure comprising blocks, additional dielectric slot structures, and a further dielectric slot structure. The stack structure includes alternating tiers of conductive and insulative structures. A block comprises a stadium structure and crest regions. The stadium structure includes staircase structures having steps comprising edges of the tiers. The additional dielectric slot structures individually extend in the first direction across a first of the crest regions and at least partially into the stadium structure. The additional dielectric slot structures are separated from one another in a second direction orthogonal to the first direction and individually vertically extend through the tiers. The further dielectric slot structure extends in the second direction across a second of the crest regions. The further dielectric slot structure intersects at least one of the additional dielectric slot structures and vertically extend through the tiers.