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    Memory Arrays And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells
    11.
    发明申请
    Memory Arrays And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells 有权

    公开(公告)号：US20210118899A1

    公开(公告)日：2021-04-22

    申请号：US16657498

    申请日：2019-10-18

    Applicant: Micron Technology, Inc.

    Inventor： Matthew J. King

    IPC: H01L27/11582 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28 ,  H01L27/11556 ,  H01L27/11519 ,  H01L21/3213 ,  H01L27/11565

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Intervening material is formed into the stack laterally-between and longitudinally-along immediately-laterally-adjacent memory block regions. The forming of the intervening material comprises forming pillars laterally-between and longitudinally-spaced-along the immediately-laterally-adjacent memory-block regions. The pillars individually extend through multiple of each of the first tiers and the second tiers. After forming the pillars, an intervening opening is formed individually alongside and between immediately-longitudinally-adjacent of the pillars. Fill material is formed in the intervening openings. Other embodiments, including structure, are disclosed.

    Gate stacks
    12.
    发明授权
    Gate stacks 有权

    公开(公告)号：US10164044B2

    公开(公告)日：2018-12-25

    申请号：US14688387

    申请日：2015-04-16

    Applicant: Micron Technology, Inc.

    Inventor： Yushi Hu ,  John Mark Meldrim ,  Eric Blomiley ,  Everett Allen McTeer ,  Matthew J. King

    IPC: H01L29/49 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

    Abstract: Some embodiments disclose a gate stack having a gate (e.g., polysilicon (poly) material) horizontally between shallow trench isolations (STIs), a tungsten silicide (WSix) material over the gate and the STIs, and a tungsten silicon nitride (WSiN) material on a top surface of the WSix material. Some embodiments disclose a gate stack having a gate between STIs, a first WSix material over the gate and the STIs, a WSiN interlayer material on a top surface of the first WSix material, and a second WSix material on a top surface of the WSiN interlayer material. Additional embodiments are disclosed.

    Memory Circuitry Comprising Strings Of Memory Cells And Method Used In Forming Memory Circuitry Comprising Strings Of Memory Cells
    14.
    发明公开
    Memory Circuitry Comprising Strings Of Memory Cells And Method Used In Forming Memory Circuitry Comprising Strings Of Memory Cells 审中-公开

    公开(公告)号：US20240355391A1

    公开(公告)日：2024-10-24

    申请号：US18618930

    申请日：2024-03-27

    Applicant: Micron Technology, Inc.

    Inventor： Pengyuan Zheng ,  Matthew J. King ,  Naveen Kaushik ,  Ravi Jadhav ,  Sidhartha Gupta

    IPC: G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

    CPC classification number: G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

    Abstract: A method used in forming memory circuitry comprising strings of memory cells comprises forming vertically-alternating tiers of different composition first and second materials. The second material is insulative. The vertically-alternating tiers comprise a stack comprising laterally-spaced memory blocks. An inter-block column of openings is formed through the vertically-alternating tiers longitudinally-along and between immediately-laterally-adjacent of the memory blocks. An intra-block column of openings is formed through the vertically-alternating tiers longitudinally-along and within individual of the memory blocks. Individual of the intra-block columns of openings are entirely within one of the individual memory blocks. A first etchant is flowed into the inter-block columns of openings and into the intra-block columns of openings to etch the first material of the first-material tiers selectively relative to the second-material tiers to form a void-space tier vertically between immediately-vertically-adjacent of the second-material tiers. The void-space tiers are filled with conductive material by flowing the conductive material or one or more precursors thereof through the inter-block columns of openings and through the intra-block columns of openings into the void-space tiers. A second etchant is flowed into the inter-block columns of openings to remove the conductive material from being between the immediately-laterally-adjacent memory blocks in individual of the filled void-space tiers. Structures independent of method are disclosed.

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