公开(公告)号：US11469187B2

公开(公告)日：2022-10-11

申请号：US16943243

申请日：2020-07-30

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Hiroaki Tokuya ,  Masahiro Shibata ,  Akihiko Ozaki ,  Satoshi Goto ,  Fumio Harima ,  Atsushi Kurokawa

IPC: H01L29/737 ,  H01L27/082 ,  H01L23/498 ,  H01L23/66 ,  H01L23/00

Abstract: At least one unit transistor is arranged over a substrate. A first wiring as a path of current that flows to each unit transistor is arranged over the at least one unit transistor. An inorganic insulation film is arranged over the first wiring. At least one first opening overlapping a partial region of the first wiring in a plan view is provided in the inorganic insulation film. An organic insulation film is arranged over the inorganic insulation film. A second wiring coupled to the first wiring through the first opening is arranged over the organic insulation film and the inorganic insulation film. In a plan view, a region in which the organic insulation film is not arranged is provided outside a region in which the first wiring is arranged. The second wiring is in contact with the inorganic insulation film outside the region in which the first wiring is arranged.

公开(公告)号：US20200152536A1

公开(公告)日：2020-05-14

申请号：US16744449

申请日：2020-01-16

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Hiroaki Tokuya ,  Yuichi Sano ,  Toshihiro Tada

IPC: H01L23/31 ,  H01L23/29 ,  H01L21/56

Abstract: An electronic component whose reliability is less likely to decrease while its thermal conductivity is maintained. A semiconductor chip is mounted on a substrate. The semiconductor chip is sealed with a sealing resin layer. The sealing resin layer includes a binder and two types of fillers having a plurality of particles dispersed in the binder. As the two types of fillers, fillers at least one of whose physical quantities, which are average particle diameter and density, are different from each other are used. The total volume density of the fillers in the sealing resin layer decreases in an upward direction from the substrate, and a portion of the sealing resin layer in a height direction of the sealing resin layer has an area in which the two types of fillers are present in a mixed manner.

公开(公告)号：US10121746B2

公开(公告)日：2018-11-06

申请号：US15814833

申请日：2017-11-16

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kazuya Kobayashi ,  Yuichi Sano ,  Daisuke Tokuda ,  Hiroaki Tokuya

IPC: H01L23/48 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532

Abstract: A semiconductor device includes a semiconductor substrate, a first metal layer, an insulation layer, an organic layer, and a second metal layer. The first metal layer, the insulation layer, the organic layer, and the second metal layer are sequentially stacked on a surface of the semiconductor substrate. The first metal layer and the second metal layer are electrically connected to each other through vias formed in the insulation layer and the organic layer. The second metal layer includes an electrode pad at a position corresponding to the positions of the vias. At the interface between the surface of the semiconductor substrate and the first metal layer, a patch portion having a trapezoidal cross-sectional shape is disposed directly below the vias.

公开(公告)号：US09991217B2

公开(公告)日：2018-06-05

申请号：US15361336

申请日：2016-11-25

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Yasunari Umemoto ,  Daisuke Tokuda ,  Tsunekazu Saimei ,  Hiroaki Tokuya

IPC: H01L29/737 ,  H01L23/00 ,  H01L29/417 ,  H01L29/732 ,  H01L29/08 ,  H01L29/66 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L24/13 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L29/0692 ,  H01L29/0817 ,  H01L29/20 ,  H01L29/205 ,  H01L29/41708 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/6631 ,  H01L29/66318 ,  H01L29/732 ,  H01L29/737 ,  H01L29/7371 ,  H01L29/7375 ,  H01L29/7378 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05666 ,  H01L2224/1134 ,  H01L2224/13013 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13026 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13563 ,  H01L2224/13611 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/07025 ,  H01L2924/10329 ,  H01L2924/10337 ,  H01L2924/10338 ,  H01L2924/13051 ,  H01L2924/13055 ,  H01L2924/1423 ,  H01L2924/351 ,  H01L2924/01079 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.