公开(公告)号：US20200287027A1

公开(公告)日：2020-09-10

申请号：US16810492

申请日：2020-03-05

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari UMEMOTO ,  Isao OBU ,  Kaoru IDENO ,  Shigeki KOYA

IPC: H01L29/737 ,  H01L29/06 ,  H01L29/08

Abstract: A semiconductor device includes a collector layer, a base layer, and an emitter layer that are disposed above a substrate. An emitter mesa layer is disposed on a partial region of the emitter layer. In a plan view, the base electrode is disposed in or on a region which does not overlap the emitter mesa layer. The base electrode allows base current to flow to the base layer. In the plan view, a first edge forming part of edges of the emitter mesa layer extends in a first direction, and a second edge forming part of edges of the base electrode faces the first edge. A gap between the first edge and the second edge in a terminal portion located in an end portion of the emitter mesa layer in the first direction is wider than a gap in an intermediate portion of the emitter mesa layer.

公开(公告)号：US20200119171A1

公开(公告)日：2020-04-16

申请号：US16710957

申请日：2019-12-11

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari UMEMOTO ,  Shigeki KOYA ,  Atsushi KUROKAWA

IPC: H01L29/737 ,  H01L29/10 ,  H01L29/66 ,  H01L29/36 ,  H01L29/08 ,  H01L29/06

Abstract: A bipolar transistor has a subcollector layer and a stack of collector, base, and emitter layers on the subcollector layer. On the subcollector layer are collector electrodes. On the base layer are base electrodes. The collector layer includes multiple doped layers with graded impurity concentrations, higher on the subcollector layer side and lower on the base layer side. Of these doped layers, the one having the highest impurity concentration is in contact with the subcollector layer and has a sheet resistance less than or equal to about nine times that of the subcollector layer.

公开(公告)号：US20200066886A1

公开(公告)日：2020-02-27

申请号：US16525400

申请日：2019-07-29

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao OBU ,  Yasunari UMEMOTO ,  Takayuki TSUTSUI ,  Satoshi TANAKA

IPC: H01L29/73 ,  H01L27/082 ,  H01L29/205 ,  H01L29/08 ,  H01L29/417 ,  H01L29/737 ,  H01L21/8252 ,  H01L21/285 ,  H01L21/306 ,  H01L21/308 ,  H01L29/66

Abstract: A first sub-collector layer functions as an inflow path of a collector current that flows in a collector layer of a heterojunction bipolar transistor. A collector ballast resistor layer having a lower doping concentration than the first sub-collector layer is disposed between the collector layer and the first sub-collector layer.

公开(公告)号：US20190158044A1

公开(公告)日：2019-05-23

申请号：US16192890

申请日：2018-11-16

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao OBU ,  Satoshi TANAKA ,  Takayuki TSUTSUI ,  Yasunari UMEMOTO

IPC: H03F3/21 ,  H03F3/19 ,  H03F1/56 ,  H03F1/02 ,  H01L27/06

Abstract: A power amplifier includes initial-stage and output-stage amplifier circuits, and initial-stage and output-stage bias circuits. The initial-stage amplifier circuit includes a first high electron mobility transistor having a source electrically connected to a reference potential, and a gate to which a radio-frequency input signal is inputted, and a first heterojunction bipolar transistor having an emitter electrically connected to a drain of the first high electron mobility transistor, a base electrically connected to the reference potential in an alternate-current fashion, and a collector to which direct-current power is supplied and from which a radio-frequency signal is outputted. The output-stage amplifier circuit includes a second heterojunction bipolar transistor having an emitter electrically connected to the reference potential, a base to which the radio-frequency signal outputted from the first heterojunction bipolar transistor is inputted, and a collector to which direct-current power is supplied and from which a radio-frequency output signal is outputted.

公开(公告)号：US20190067460A1

公开(公告)日：2019-02-28

申请号：US16171088

申请日：2018-10-25

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari UMEMOTO ,  Atsushi KUROKAWA ,  Tsunekazu SAIMEI

IPC: H01L29/737 ,  H01L29/12 ,  H01L29/66 ,  H01L29/36 ,  H01L29/08 ,  H01L29/205 ,  H01L29/10

Abstract: In a bipolar transistor, a collector layer includes three semiconductor layers: an n-type GaAs layer (Si concentration: about 5×1015 cm−3, thickness: about 350 nm), a p-type GaAs layer (C concentration: about 4.5×1015 cm−3, thickness: about 100 nm, sheet concentration: 4.5×1010 cm−2), and an n-type GaAs layer Si concentration: about 5×1015 cm−3, thickness: about 500 nm. The sheet concentration of the p-type GaAs layer is set to less than 1×1011 cm−2.

公开(公告)号：US20140361406A1

公开(公告)日：2014-12-11

申请号：US14469674

申请日：2014-08-27

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Satoshi SASAKI ,  Yasunari UMEMOTO ,  Yasuo OSONE ,  Tsutomu KOBORI ,  Chushiro KUSANO ,  Isao OHBU ,  Kenji SASAKI

IPC: H01L29/73 ,  H01L49/02 ,  H01L29/08 ,  H01L27/06

CPC classification number: H01L29/7304 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L25/042 ,  H01L27/0605 ,  H01L27/067 ,  H01L28/40 ,  H01L29/0808 ,  H01L29/7371 ,  H01L2223/6627 ,  H01L2223/6644 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/10336 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/19032 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A radio communication device includes a power amplifier having a semiconductor device formed with a plurality of unit transistors. Base electrodes of the unit transistors are connected with each other by a base line, and an input capacitor is connected to the base line such that the input capacitor is commonly and electrically connected to the base electrodes of a plurality of the unit transistors.

Abstract translation: 无线电通信装置包括具有形成有多个单位晶体管的半导体器件的功率放大器。 单元晶体管的基极通过基线相互连接，输入电容器连接到基极线，使得输入电容器与多个单位晶体管的基极电连接。

公开(公告)号：US20210234026A1

公开(公告)日：2021-07-29

申请号：US17229564

申请日：2021-04-13

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari UMEMOTO ,  Shigeki KOYA ,  Atsushi KUROKAWA

IPC: H01L29/737 ,  H01L29/06 ,  H01L29/08 ,  H01L29/36 ,  H01L29/66 ,  H01L29/10

Abstract: A bipolar transistor comprising a subcollector layer, and a collector layer on the subcollector layer. The collector layer includes a plurality of doped layers. The plurality of doped layers includes a first doped layer that has a highest impurity concentration thereamong and is on a side of or in contact with the subcollector layer. Also, the first doped layer includes a portion that extends beyond at least one edge of the plurality of doped layers in a cross-sectional view.

公开(公告)号：US20210184022A1

公开(公告)日：2021-06-17

申请号：US17189043

申请日：2021-03-01

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari UMEMOTO ,  Daisuke TOKUDA ,  Tsunekazu SAIMEI ,  Hiroaki TOKUYA

IPC: H01L29/737 ,  H01L29/417 ,  H01L29/732 ,  H01L23/00 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/20 ,  H01L29/205

Abstract: A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.

公开(公告)号：US20210126591A1

公开(公告)日：2021-04-29

申请号：US17143940

申请日：2021-01-07

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao OBU ,  Yasunari UMEMOTO ,  Masahiro SHIBATA ,  Kenichi NAGURA

IPC: H03F1/52 ,  H01L23/00 ,  H01L29/04 ,  H03F3/213 ,  H01L29/737 ,  H01L27/02 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/205 ,  H01L29/06 ,  H01L21/265 ,  H01L29/417 ,  H01L29/423 ,  H01L23/48 ,  H01L29/861 ,  H01L21/768 ,  H03F3/195 ,  H01L21/02 ,  H01L29/36 ,  H01L29/207 ,  H01L29/45 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/027 ,  H01L29/66 ,  H01L21/306 ,  H01L21/311 ,  H03F1/56

Abstract: A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.

公开(公告)号：US20210098585A1

公开(公告)日：2021-04-01

申请号：US17027618

申请日：2020-09-21

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari UMEMOTO ,  Shaojun MA ,  Shigeki KOYA

IPC: H01L29/423 ,  H03F3/21 ,  H03F1/02 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/737

Abstract: A collector layer is disposed on a substrate. The collector layer is a continuous region when viewed in plan. A base layer is disposed on the collector layer. An emitter layer is disposed on the base layer. An emitter mesa layer is disposed on the emitter layer. Two base electrodes are located outside the emitter mesa layer and within the base layer when viewed in plan. The two base electrodes are electrically connected to the base layer. Two capacitors are disposed on or above the substrate. Each of the two capacitors is connected between a corresponding one of the two base electrodes and a first line above the substrate. Two resistance elements are disposed on or above the substrate. Each of the two resistance elements is connected between a corresponding one of the two base electrodes and a second line on or above the substrate.