公开(公告)号：US20130320400A1

公开(公告)日：2013-12-05

申请号：US13895228

申请日：2013-05-15

Applicant: NXP B.V.

Inventor： Godefridus Adrianus Maria HURKX ,  Jeroen Antoon CROON ,  Johannes Josephus Theodorus Marinus Donkers ,  Jan Sonsky ,  Stephen John SQUE ,  Andreas Bernardus Maria JANSMAN ,  Markus MUELLER ,  Stephan HEIL ,  Tim BOETTCHER

IPC: H01L29/47 ,  H01L29/40

CPC classification number: H01L29/475 ,  H01L21/02362 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/417 ,  H01L29/42316 ,  H01L29/7787 ,  H01L29/7788 ,  H01L29/872

Abstract: Disclosed is a semiconductor device comprising a group 13 nitride heterojunction comprising a first layer having a first bandgap and a second layer having a second bandgap, wherein the first layer is located between a substrate and the second layer; and a Schottky electrode and a first further electrode each conductively coupled to a different area of the heterojunction, said Schottky electrode comprising a central region and an edge region, wherein the element comprises a conductive barrier portion located underneath said edge region only of the Schottky electrode for locally increasing the Schottky barrier of the Schottky electrode. A method of manufacturing such a semiconductor device is also disclosed.

Abstract translation: 公开了一种包括13族氮化物异质结的半导体器件，其包括具有第一带隙的第一层和具有第二带隙的第二层，其中第一层位于衬底和第二层之间; 以及肖特基电极和第一另外的电极，每个导体耦合到所述异质结的不同区域，所述肖特基电极包括中心区域和边缘区域，其中所述元件包括仅位于所述肖特基电极的所述边缘区域下方的导电阻挡部分 用于局部增加肖特基电极的肖特基势垒。 还公开了制造这种半导体器件的方法。

公开(公告)号：US10134860B2

公开(公告)日：2018-11-20

申请号：US15456963

申请日：2017-03-13

Applicant: NXP B.V.

Inventor： Jan Sonsky ,  Viet Thanh Dinh ,  Jan Claes

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes a first dielectric layer on a substrate, the first dielectric layer including a first dielectric portion over a first doped well region of a first conductivity type and a second dielectric portion over a second doped well region of a second conductivity type, and a second dielectric layer on the substrate directly adjacent the first dielectric layer. The second dielectric layer is over the second doped well region. A first conductive gate structure is over the first and second dielectric layers. A third dielectric layer is on the substrate over the second doped well region and separated a first distance from the second dielectric layer. A second conductive gate structure is over the third dielectric layer. A third doped region of the second conductivity type is implanted in the second doped well region a second distance from the third dielectric layer and the second conductive gate structure.

公开(公告)号：US20170154988A1

公开(公告)日：2017-06-01

申请号：US15356509

申请日：2016-11-18

Applicant: NXP B.V.

Inventor： Godefridus Adrianus Maria Hurkx ,  Johannes Josephus Theodorus Marinus Donkers ,  Jan Sonsky ,  Jeroen Antoon Croon

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/872 ,  H01L29/66 ,  H01L29/20

CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/423 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/872

Abstract: A semiconductor device and a method of making the same is disclosed. The device includes a substrate having an AlGaN layer located on a GaN layer for forming a two dimensional electron gas at an interface between the AlGaN layer and the GaN layer. The device also includes a plurality of contacts. At least one of the contacts includes an ohmic contact portion located on a major surface of the substrate. The ohmic contact portion comprises a first electrically conductive material. The at least one of the contacts also includes a trench extending down into the substrate from the major surface. The trench passes through the AlGaN layer and into the GaN layer. The trench is at least partially filled with a second electrically conductive material. The second electrically conductive material is a different electrically conductive material to the first electrically conductive material.

公开(公告)号：US09608514B2

公开(公告)日：2017-03-28

申请号：US14613235

申请日：2015-02-03

Applicant: NXP B.V.

Inventor： Henricus Cornelis Johannes Buthker ,  Matthias Rose ,  Philip Rutter ,  Jan Sonsky

IPC: H02M7/06 ,  H02H9/08 ,  H02M1/42 ,  H02M3/155 ,  H02M1/00

CPC classification number: H02M1/4225 ,  H02M3/155 ,  H02M7/06 ,  H02M2001/0048 ,  Y02B70/126 ,  Y02B70/1491 ,  Y02P80/112

Abstract: Embodiments relate to a diode circuit which uses a Schottky diode. A parallel bypass branch has a switch and bypass diode in series. The operation of the switch is dependent on the voltage across the Schottky diode so that the bypass function is only effective when a desired voltage is reached. The diode circuit can be used as a replacement for a single diode, and provides bypass current protection preferably without requiring any external control input.

公开(公告)号：US20160079282A1

公开(公告)日：2016-03-17

申请号：US14946064

申请日：2015-11-19

Applicant: NXP B.V.

Inventor： Jan Sonsky

IPC: H01L27/12 ,  H01L29/267 ,  H01L29/06

CPC classification number: H01L29/0649 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/76264 ,  H01L21/76283 ,  H01L27/1207 ,  H01L29/267

Abstract: A method of manufacturing a semiconductor device includes forming trench isolation structures, exposing some of the trench isolation structures 28 to leave others 30 masked, and then selectively etching a buried layer to form a cavity 32 under an active device region 34. The active device region 34 is supported by support regions in the exposed trenches 28. The buried layer may be a SiGe layer on a Si substrate.

Abstract translation: 制造半导体器件的方法包括形成沟槽隔离结构，暴露一些沟槽隔离结构28以使另外30个被掩蔽，然后选择性地蚀刻掩埋层，以在有源器件区域34下方形成空腔32.有源器件区域 34由暴露的沟槽28中的支撑区域支撑。掩埋层可以是Si衬底上的SiGe层。

公开(公告)号：US20160020296A1

公开(公告)日：2016-01-21

申请号：US14714927

申请日：2015-05-18

Applicant: NXP B.V.

Inventor： Godefridus Adrianus Maria Hurkx ,  Jeroen Antoon Croon ,  Johannes Josephus Theodorus Marinus Donkers ,  Jan Sonsky ,  Stephen John Sque ,  Andreas Bernardus Maria Jansman ,  Markus Mueller ,  Stephan Heil ,  Tim Boettcher

IPC: H01L29/47 ,  H01L21/02 ,  H01L29/40

CPC classification number: H01L29/475 ,  H01L21/02362 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/417 ,  H01L29/42316 ,  H01L29/7787 ,  H01L29/7788 ,  H01L29/872

Abstract: Disclosed is a semiconductor device comprising a group 13 nitride heterojunction comprising a first layer having a first bandgap and a second layer having a second bandgap, wherein the first layer is located between a substrate and the second layer; and a Schottky electrode and a first further electrode each conductively coupled to a different area of the heterojunction, said Schottky electrode comprising a central region and an edge region, wherein the element comprises a conductive barrier portion located underneath said edge region only of the Schottky electrode for locally increasing the Schottky barrier of the Schottky electrode. A method of manufacturing such a semiconductor device is also disclosed.

公开(公告)号：US09177852B2

公开(公告)日：2015-11-03

申请号：US14449522

申请日：2014-08-01

Applicant: NXP B.V.

Inventor： Peter Gerard Steeneken ,  Roel Daamen ,  Gerard Koops ,  Jan Sonsky ,  Evelyne Gridelet ,  Coenraad Cornelis Tak

IPC: H01L21/70 ,  H01L21/762 ,  H01L21/8238

CPC classification number: H01L21/76232 ,  H01L21/76224 ,  H01L21/823878

Abstract: An isolated semiconductor circuit comprising: a first sub-circuit and a second sub-circuit; a backend that includes an electrically isolating connector between the first and second sub-circuits; a lateral isolating trench between the semiconductor portions of the first and second sub-circuits, wherein the lateral isolating trench extends along the width of the semiconductor portions of the first and second sub-circuits, wherein one end of the isolating trench is adjacent the backend, and wherein the isolating trench is filled with an electrically isolating material.

Abstract translation: 一种隔离半导体电路，包括：第一子电路和第二子电路; 后端，其包括在所述第一和第二子电路之间的电隔离连接器; 在所述第一和第二子电路的半导体部分之间的横向隔离沟槽，其中所述横向隔离沟槽沿着所述第一和第二子电路的半导体部分的宽度延伸，其中所述隔离沟槽的一端与所述后端 ，并且其中所述隔离沟槽填充有电绝缘材料。

公开(公告)号：US09171837B2

公开(公告)日：2015-10-27

申请号：US14094890

申请日：2013-12-03

Applicant: NXP B.V.

Inventor： Philip Rutter ,  Jan Sonsky ,  Matthias Rose

IPC: H03K3/00 ,  H01L27/06 ,  H01L23/495 ,  H03K17/567 ,  H01L23/482 ,  H01L25/07

CPC classification number: H01L27/0629 ,  H01L23/4824 ,  H01L23/49531 ,  H01L23/49562 ,  H01L23/49575 ,  H01L25/072 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49171 ,  H01L2924/12032 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/30107 ,  H03K17/567 ,  H01L2924/00

Abstract: A cascode circuit arrangement has a low voltage MOSFET and a depletion mode power device mounted on a substrate (for example a ceramic substrate), which can then be placed in a semiconductor package. This enables inductances to be reduced, and can enable a three terminal packages to be used if desired.

Abstract translation: 共源共栅电路装置具有安装在衬底（例如陶瓷衬底）上的低电压MOSFET和耗尽型功率器件，然后可将其放置在半导体封装中。 这使得能够减小电感，并且如果需要，可以使用三端子封装。

公开(公告)号：US09064847B2

公开(公告)日：2015-06-23

申请号：US13895228

申请日：2013-05-15

Applicant: NXP B.V.

Inventor： Godefridus Andrianus Maria Hurkx ,  Jeroen Antoon Croon ,  Johannes Josephus Theodorus Marinus Donkers ,  Jan Sonsky ,  Stephen John Sque ,  Andreas Bernardus Maria Jansman ,  Markus Mueller ,  Stephan Heil ,  Tim Boettcher

IPC: H01L29/47 ,  H01L29/417 ,  H01L29/423 ,  H01L29/778 ,  H01L29/872 ,  H01L29/40 ,  H01L21/02 ,  H01L29/20

CPC classification number: H01L29/475 ,  H01L21/02362 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/417 ,  H01L29/42316 ,  H01L29/7787 ,  H01L29/7788 ,  H01L29/872

Abstract: Disclosed is a semiconductor device comprising a group 13 nitride heterojunction comprising a first layer having a first bandgap and a second layer having a second bandgap, wherein the first layer is located between a substrate and the second layer; and a Schottky electrode and a first further electrode each conductively coupled to a different area of the heterojunction, said Schottky electrode comprising a central region and an edge region, wherein the element comprises a conductive barrier portion located underneath said edge region only of the Schottky electrode for locally increasing the Schottky barrier of the Schottky electrode. A method of manufacturing such a semiconductor device is also disclosed.

Abstract translation: 公开了一种包括13族氮化物异质结的半导体器件，其包括具有第一带隙的第一层和具有第二带隙的第二层，其中第一层位于衬底和第二层之间; 以及肖特基电极和第一另外的电极，每个导体耦合到所述异质结的不同区域，所述肖特基电极包括中心区域和边缘区域，其中所述元件包括仅位于所述肖特基电极的所述边缘区域下方的导电阻挡部分 用于局部增加肖特基电极的肖特基势垒。 还公开了制造这种半导体器件的方法。

公开(公告)号：US20140167822A1

公开(公告)日：2014-06-19

申请号：US14094890

申请日：2013-12-03

Applicant: NXP B.V.

Inventor： Philip Rutter ,  Jan Sonsky ,  Matthias Rose

IPC: H01L27/06

CPC classification number: H01L27/0629 ,  H01L23/4824 ,  H01L23/49531 ,  H01L23/49562 ,  H01L23/49575 ,  H01L25/072 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49171 ,  H01L2924/12032 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/30107 ,  H03K17/567 ,  H01L2924/00

Abstract: A cascode circuit arrangement has a low voltage MOSFET and a depletion mode power device mounted on a substrate (for example a ceramic substrate), which can then be placed in a semiconductor package. This enables inductances to be reduced, and can enable a three terminal packages to be used if desired.

Abstract translation: 共源共栅电路装置具有安装在衬底（例如陶瓷衬底）上的低电压MOSFET和耗尽型功率器件，然后可将其放置在半导体封装中。 这使得能够减小电感，并且如果需要，可以使用三端子封装。