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公开(公告)号：US08907835B2
公开(公告)日：2014-12-09
申请号：US13850817
申请日：2013-03-26
Applicant: Olympus Corporation , Denso Corporation
Inventor： Takanori Tanaka
CPC classification number: H04N5/335 , H03M1/12 , H03M1/123 , H03M1/502 , H03M1/60 , H04N5/374 , H04N5/378
Abstract: An A/D conversion circuit may include: a delay circuit that includes a plurality of delay units having a first pulse input terminal, a pulse output terminal, and an analog signal input terminal, wherein each first pulse input terminal of the plurality of delay units is connected to one of the pulse output terminals corresponding to the plurality of delay units, and a pulse output signal input to the first pulse input terminal is delayed in accordance with an analog signal input to the analog signal input terminal and output from the pulse output terminal, and one of the plurality of delay units has a second pulse input terminal to which a pulse signal is input from outside; a state variation detection circuit; and an encoding signal latch circuit.
Abstract translation: A / D转换电路可以包括：延迟电路，包括具有第一脉冲输入端，脉冲输出端和模拟信号输入端的多个延迟单元，其中多个延迟单元中的每个第一脉冲输入端 连接到对应于多个延迟单元的一个脉冲输出端子，并且输入到第一脉冲输入端子的脉冲输出信号根据输入到模拟信号输入端的模拟信号被延迟并从脉冲输出端输出 并且所述多个延迟单元中的一个具有从外部输入脉冲信号的第二脉冲输入端子; 状态变化检测电路; 和编码信号锁存电路。
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公开(公告)号：US11304589B2
公开(公告)日：2022-04-19
申请号：US16826825
申请日：2020-03-23
Applicant: OLYMPUS CORPORATION
Inventor： Takanori Tanaka
Abstract: An endoscope includes: an imager; a transmission path configured to connect a controller and the imager with each other; a superimposed signal generating circuit configured to generate, as a superimposed signal, a signal obtained by associating High and Low of a pulsed data signal with a change in a pulse width of a pulsed reference clock signal; a parallel-serial converter circuit configured to perform parallel-serial conversion on the imaging signal; a PLL circuit configured to generate a multiplied clock signal; a restoring circuit configured to restore, based on the superimposed signal and the multiplied clock signal, the reference clock signal and the data signal contained in the superimposed signal; and a timing generating circuit configured to generate, based on the reference clock signal and the data signal, a drive signal for driving the imager.
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公开(公告)号：US20210177241A1
公开(公告)日：2021-06-17
申请号：US17189773
申请日：2021-03-02
Applicant: OLYMPUS CORPORATION
Inventor： Takanori Tanaka , Masato Osawa
Abstract: In an imaging system, an image transmission circuit is configured to output image data to a signal line in a first mode. A signal reception circuit is configured to receive a clock control signal for adjusting a frequency of a camera clock from an image reception unit in a second mode. A signal output circuit is configured to output a first electric potential and the clock control signal to the signal line. The first electric potential corresponds to a signal level that is not included in a range of a signal level of the image data output to the signal line. A communication control circuit is configured to switch communication modes from the first mode to the second mode when the communication control circuit detects the first electric potential in the first mode.
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公开(公告)号：US20180220879A1
公开(公告)日：2018-08-09
申请号：US15939740
申请日：2018-03-29
Applicant: OLYMPUS CORPORATION
Inventor： Takatoshi Igarashi , Noriyuki Fujimori , Makoto Ono , Masashi Saito , Satoru Adachi , Nana Akahane , Takanori Tanaka , Katsumi Hosogai
IPC: A61B1/05 , A61B1/045 , A61B1/06 , A61B1/00 , H04N5/378 , H04N5/345 , H04N5/376 , H04N7/10 , H01L27/146 , H01L21/66
CPC classification number: A61B1/05 , A61B1/00195 , A61B1/045 , A61B1/063 , A61B1/0638 , H01L22/32 , H01L25/065 , H01L25/07 , H01L25/16 , H01L25/18 , H01L27/14 , H01L27/146 , H01L27/14618 , H01L27/14634 , H01L27/14636 , H01L27/1469 , H04N5/2256 , H04N5/23203 , H04N5/345 , H04N5/3765 , H04N5/378 , H04N5/379 , H04N7/102 , H04N2005/2255
Abstract: An imaging device includes: a first chip including a light receiving unit, and a read circuit; a second chip including a timing control circuit, an A/D conversion circuit, and a cable transmission circuit; and a connection unit configured to connect the first and the second chips. The read circuit includes a column read circuit and a horizontal selection circuit, and a vertical selection circuit. The connection unit of the first chip is provided in a first area along a side of the rectangular light receiving unit, and in a second area adjacent to the column read circuit, the horizontal selection circuit, and the vertical selection circuit. The connection unit of the second chip is provided in a third area around the timing control circuit, the A/D conversion circuit, and the cable transmission circuit and in a fourth area adjacent to the timing control circuit and the A/D conversion circuit.
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公开(公告)号：US20130208160A1
公开(公告)日：2013-08-15
申请号：US13850817
申请日：2013-03-26
Applicant: Olympus Corporation , Denso Corporation
Inventor： Takanori Tanaka
CPC classification number: H04N5/335 , H03M1/12 , H03M1/123 , H03M1/502 , H03M1/60 , H04N5/374 , H04N5/378
Abstract: An A/D conversion circuit may include: a delay circuit that includes a plurality of delay units having a first pulse input terminal, a pulse output terminal, and an analog signal input terminal, wherein each first pulse input terminal of the plurality of delay units is connected to one of the pulse output terminals corresponding to the plurality of delay units, and a pulse output signal input to the first pulse input terminal is delayed in accordance with an analog signal input to the analog signal input terminal and output from the pulse output terminal, and one of the plurality of delay units has a second pulse input terminal to which a pulse signal is input from outside; a state variation detection circuit; and an encoding signal latch circuit.
Abstract translation: A / D转换电路可以包括：延迟电路，包括具有第一脉冲输入端的多个延迟单元，脉冲输出端和模拟信号输入端，其中多个延迟单元中的每个第一脉冲输入端 连接到对应于多个延迟单元的一个脉冲输出端子，并且输入到第一脉冲输入端子的脉冲输出信号根据输入到模拟信号输入端的模拟信号被延迟并从脉冲输出端输出 并且所述多个延迟单元中的一个具有从外部输入脉冲信号的第二脉冲输入端子; 状态变化检测电路; 和编码信号锁存电路。
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Patent Agency Ranking
公开(公告)号：US20130105665A1
公开(公告)日：2013-05-02
申请号：US13662596
申请日：2012-10-29
Applicant: OLYMPUS CORPORATION
Inventor： Takanori Tanaka , Susumu Yamazaki
IPC: H01L27/146
CPC classification number: H04N5/3765 , H03M1/123 , H03M1/502 , H04N5/378
Abstract: In this solid-state imaging device, an output signal of any one of a plurality of delay units that output signals of logic states in accordance with a level of a pixel signal is input to an input terminal of a latch circuit that latches a logic state of the output signal. A NAND circuit and an INV circuit stop until a control signal output timing at which a control signal in accordance with the level of the pixel signal is output, and operate after the control signal output timing. A switch circuit outputs the output signal of the one of the plurality of delay units through a signal line from an output terminal until the control signal output timing, and switches a connection at a latch timing after a predetermined time elapses from the control signal output timing such that the NAND circuit and the INV circuit latch the logic state of the output signal of the one of the plurality of delay units.
Abstract translation: 在该固态成像装置中，将根据像素信号的电平输出逻辑状态的信号的多个延迟单元中的任一个的输出信号输入到锁存逻辑状态的锁存电路的输入端子 的输出信号。 NAND电路和INV电路停止，直到输出根据像素信号的电平的控制信号的控制信号输出定时，并且在控制信号输出定时之后操作。 开关电路通过信号线从输出端子输出多个延迟单元中的一个延迟单元的输出信号，直到控制信号输出定时，并且在从控制信号输出定时经过预定时间之后的锁存定时处切换连接 使得NAND电路和INV电路锁存多个延迟单元之一的输出信号的逻辑状态。
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公开(公告)号：US11736092B2
公开(公告)日：2023-08-22
申请号：US17893832
申请日：2022-08-23
Applicant: OLYMPUS CORPORATION
Inventor： Takanori Tanaka , Shuzo Hiraide
CPC classification number: H03H11/16 , H03L7/0814 , G11C7/222
Abstract: In a phase adjustment circuit, a binary circuit is configured to output a binary signal on the basis of an edge of a video signal. A phase-delayed clock signal generation circuit is configured to generate a phase-delayed clock signal having a later phase than a phase of a clock signal by a first delay amount. A delay time control circuit is configured to cause a phase of the binary signal and the phase of the phase-delayed clock signal to match each other by adjusting the first delay amount. A sampling signal generation circuit is configured to generate a sampling signal having a later phase than the phase of the clock signal by a second delay amount. The second delay amount is in accordance with both a phase shift amount, which is based on the clock signal, and the first delay amount.
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公开(公告)号：US09609257B2
公开(公告)日：2017-03-28
申请号：US14644893
申请日：2015-03-11
Applicant: OLYMPUS CORPORATION
Inventor： Takanori Tanaka
IPC: H03M1/34 , H04N5/378 , H01L27/146 , H04N5/369 , H04N5/357
CPC classification number: H04N5/378 , H01L27/14636 , H04N5/357 , H04N5/369
Abstract: A solid-state imaging device includes: a first substrate; a second substrate; a pixel unit in which pixels are disposed in a matrix; and an A/D conversion unit that is disposed for every columns of the pixels and counts a count clock for only a period according to a magnitude of the pixel signal. The A/D conversion unit includes: counter units that is provided in one of the first substrate and the second substrate and generates n-bit count signals; memory units that is provided in the other of the first substrate and the second substrate and holds the count signals and outputs the held count signals to horizontal signal transfer lines; and a connection unit that connects each counter unit to a corresponding one of the memory units and simultaneously transfer the count signals from at least two counter units to at least two memory units.
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公开(公告)号：US09287890B2
公开(公告)日：2016-03-15
申请号：US14676414
申请日：2015-04-01
Applicant: OLYMPUS CORPORATION
Inventor： Takanori Tanaka
Abstract: An analog-to-digital (AD) converter has a latch section having latch units, a capacitor, and a latch control signal line connected to the latch units. A third voltage less than a first voltage and greater than a second voltage is applied as a power supply voltage to the latch units. When the capacitor is electrically connected to the latch control signal line, a potential of the latch control signal line becomes greater than or equal to the third voltage. Only when the electrical connection between the capacitor and the latch control signal line is disconnected, the first voltage is applied to the capacitor and the second voltage is applied to the latch control signal line. When the potential of the latch control signal line becomes greater than or equal to the third voltage, the latch units latch clock signals.
Abstract translation: 模数（AD）转换器具有锁存单元，具有锁存单元，电容器和连接到锁存单元的锁存控制信号线。 施加小于第一电压且大于第二电压的第三电压作为电源电压施加到锁存单元。 当电容器电连接到锁存控制信号线时，锁存控制信号线的电位变得大于或等于第三电压。 只有当电容器和锁存器控制信号线之间的电连接断开时，第一个电压被施加到电容器，第二个电压被施加到锁存控制信号线。 当锁存控制信号线的电位变得大于或等于第三电压时，锁存单元锁存时钟信号。
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公开(公告)号：US20150189213A1
公开(公告)日：2015-07-02
申请号：US14644893
申请日：2015-03-11
Applicant: OLYMPUS CORPORATION
Inventor： Takanori Tanaka
CPC classification number: H04N5/378 , H01L27/14636 , H04N5/357 , H04N5/369
Abstract: A solid-state imaging device includes: a first substrate; a second substrate; a pixel unit in which pixels are disposed in a matrix; and an A/D conversion unit that is disposed for every columns of the pixels and counts a count clock for only a period according to a magnitude of the pixel signal. The A/D conversion unit includes: counter units that is provided in one of the first substrate and the second substrate and generates n-bit count signals; memory units that is provided in the other of the first substrate and the second substrate and holds the count signals and outputs the held count signals to horizontal signal transfer lines; and a connection unit that connects each counter unit to a corresponding one of the memory units and simultaneously transfer the count signals from at least two counter units to at least two memory units.
Abstract translation: 固态成像装置包括：第一基板; 第二基板; 像素单元，其中像素被布置在矩阵中; 以及A / D转换单元，其被设置用于每列像素，并且根据像素信号的大小仅计数一个周期的计数时钟。 A / D转换单元包括：设置在第一基板和第二基板之一中的计数器单元，并产生n位计数信号; 存储单元，设置在第一基板和第二基板的另一个中，并保持计数信号，并将保持的计数信号输出到水平信号传输线; 以及连接单元，其将每个计数器单元连接到相应的一个存储单元，并且将来自至少两个计数器单元的计数信号同时传送到至少两个存储器单元。
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