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    MULTILAYER CERAMIC CAPACITOR
    12.
    发明申请
    MULTILAYER CERAMIC CAPACITOR 审中-公开
    多层陶瓷电容器

    公开(公告)号：US20150310990A1

    公开(公告)日：2015-10-29

    申请号：US14261373

    申请日：2014-04-24

    Applicant: Qualcomm Incorporated

    Inventor： Lalan Jee Mishra ,  Shree Krishna Pandey ,  Nazanin Darbanian ,  John David Eaton

    IPC: H01G4/30

    CPC classification number: H01G4/30 ,  H01G4/012 ,  H01G4/12 ,  H01G4/232

    Abstract: Aspects of a method of manufacturing a capacitor are provided. The method includes layering a plurality of dielectric plates. The plurality of dielectric plates includes a first dielectric plate having a first conductive region and a second conductive region on a surface of the first dielectric plate. The method further includes forming an inner electrode through an axis of the layered plurality of dielectric plates. The inner electrode electrically couples to the first conductive region on the surface of the first dielectric plate. The method further includes forming an outer electrode, where the outer electrode electrically couples to the second conductive region on the surface of the first dielectric plate.

    Abstract translation: 提供制造电容器的方法的方面。 该方法包括层叠多个电介质板。 多个电介质板包括在第一电介质板的表面上具有第一导电区域和第二导电区域的第一电介质板。 该方法还包括通过层叠的多个电介质板的轴线形成内部电极。 内部电极电耦合到第一电介质板的表面上的第一导电区域。 该方法还包括形成外部电极，其中外部电极电耦合到第一电介质板的表面上的第二导电区域。

    Horizontal interconnects crosstalk optimization
    14.
    发明授权
    Horizontal interconnects crosstalk optimization 有权
    水平互连串扰优化

    公开(公告)号：US09038011B2

    公开(公告)日：2015-05-19

    申请号：US13926830

    申请日：2013-06-25

    Applicant: QUALCOMM Incorporated

    Inventor： Shree Krishna Pandey ,  Changyu Sun

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5036 ,  G06F17/5077 ,  G06F2217/82

    Abstract: A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus generates a plurality of interconnect patterns for a set of longitudinal channels that are occupied by horizontal interconnects. Each interconnect pattern may be different from the other interconnect patterns. Each interconnect pattern may define relative locations for the set of horizontal interconnects and gap channels. Highest crosstalk is determined for each of the interconnect patterns and the interconnect pattern with the minimum highest crosstalk is selected as a preferred pattern. The highest crosstalk may comprise far-end crosstalk or near-end crosstalk and may be calculated for a range of frequencies or for a plurality of frequencies. The crosstalk may be calculated by modeling the interconnects as transmission lines.

    Abstract translation: 提供了一种用于无线通信的方法，装置和计算机程序产品。 该装置为由水平互连占据的一组纵向通道产生多个互连图案。 每个互连图案可以不同于其他互连图案。 每个互连图案可以限定该组水平互连和间隙通道的相对位置。 对于每个互连图案确定最高串扰，并且选择具有最小最高串扰的互连图案作为优选图案。 最高串扰可能包括远端串扰或近端串扰，并且可以针对频率范围或多个频率来计算。 可以通过将互连模型化为传输线来计算串扰。

    Multi-wire signaling with matched propagation delay among wire pairs
    16.
    发明授权
    Multi-wire signaling with matched propagation delay among wire pairs 有权
    电线对之间具有匹配传播延迟的多线信号

    公开(公告)号：US09521058B2

    公开(公告)日：2016-12-13

    申请号：US15097027

    申请日：2016-04-12

    Applicant: QUALCOMM Incorporated

    Inventor： Shree Krishna Pandey ,  Arun Chandra Kundu ,  George Alan Wiley ,  Chulkyu Lee

    IPC: H04L25/02 ,  H04L12/26 ,  H04L7/00 ,  H04B3/00 ,  H04B3/462 ,  H04B3/54

    CPC classification number: H04L43/087 ,  G06F13/40 ,  H04B3/00 ,  H04B3/462 ,  H04B3/542 ,  H04L7/0041 ,  H04L25/0264 ,  H04L25/14

    Abstract: In a multi-wire channel that includes at least three wires, each unique wire pair of the multi-wire channel has approximately the same signal propagation time. In this way, jitter can be mitigated in the multi-wire channel for signaling where, for a given data transfer, a differential signal is transmitting on a particular pair of the wires and every other wire is floating. In some implementations, matching of the signal propagation times involves providing additional delay for at least one of the wires. The additional delay is provided using passive signal delay techniques and/or active signal delay techniques.

    Abstract translation: 在包括至少三条线的多线通道中，多线通道的每条独特的线对具有大致相同的信号传播时间。 以这种方式，可以在用于信令的多线信道中减轻抖动，其中对于给定的数据传输，差分信号在特定的一对导线上传输，并且每隔一个线路浮动。 在一些实现中，信号传播时间的匹配涉及为至少一条电线提供额外的延迟。 使用无源信号延迟技术和/或有源信号延迟技术来提供额外的延迟。

    MULTI-WIRE SIGNALING WITH MATCHED PROPAGATION DELAY AMONG WIRE PAIRS
    17.
    发明申请
    MULTI-WIRE SIGNALING WITH MATCHED PROPAGATION DELAY AMONG WIRE PAIRS 有权
    多线对信号通过配对传播延迟线对

    公开(公告)号：US20150381340A1

    公开(公告)日：2015-12-31

    申请号：US14315142

    申请日：2014-06-25

    Applicant: QUALCOMM Incorporated

    Inventor： Shree Krishna Pandey ,  Arun Chandra Kundu ,  George Alan Wiley ,  Chulkyu Lee

    IPC: H04L7/00 ,  H04B3/462 ,  H04B3/54

    CPC classification number: H04L7/0041 ,  H04B3/00 ,  H04B3/462 ,  H04B3/542 ,  H04L25/0264

    Abstract: In a multi-wire channel that includes at least three wires, each unique wire pair of the multi-wire channel has approximately the same signal propagation time. In this way, jitter can be mitigated in the multi-wire channel for signaling where, for a given data transfer, a differential signal is transmitting on a particular pair of the wires and every other wire is floating. In some implementations, matching of the signal propagation times involves providing additional delay for at least one of the wires. The additional delay is provided using passive signal delay techniques and/or active signal delay techniques.

    Abstract translation: 在包括至少三条电线的多线通道中，多线通道的每条唯一的线对具有大致相同的信号传播时间。 以这种方式，可以在用于信令的多线信道中减轻抖动，其中对于给定的数据传输，差分信号在特定的一对导线上传输，并且每隔一个线路浮动。 在一些实现中，信号传播时间的匹配涉及为至少一条电线提供额外的延迟。 使用无源信号延迟技术和/或有源信号延迟技术来提供额外的延迟。

    Memory interface offset signaling
    18.
    发明授权
    Memory interface offset signaling 有权
    存储器接口偏移信号

    公开(公告)号：US09177623B2

    公开(公告)日：2015-11-03

    申请号：US13842515

    申请日：2013-03-15

    Applicant: QUALCOMM Incorporated

    Inventor： Shree Krishna Pandey ,  Dexter T. Chun

    IPC: G06F1/10 ,  G11C7/22 ,  G06F13/16 ,  G06F13/42

    CPC classification number: G11C7/227 ,  G06F1/10 ,  G06F13/1689 ,  G06F13/4243

    Abstract: A memory interface includes circuitry configured for applying a variable delay to a portion of a data signal and applying a variable delay to a data strobe. The delayed data strobe samples the delayed portion of the data signal. Delayed portions of the data signal are spaced away from non-delayed portions of the data signal by alternating the routing of delayed bits and non-delayed bits of the data signal. A training block determines and sets a value of the variable delay corresponding to a largest value of a number of recorded eye aperture widths.

    Abstract translation: 存储器接口包括经配置以将可变延迟应用于数据信号的一部分并将可变延迟应用于数据选通的电路。 延迟数据选通对数据信号的延迟部分进行采样。 通过交替数据信号的延迟位和非延迟位的路由，数据信号的延迟部分与数据信号的非延迟部分间隔开。 训练块确定并设置与记录的眼孔宽度的数量的最大值相对应的可变延迟的值。

    MEMORY INTERFACE OFFSET SIGNALING
    19.
    发明申请
    MEMORY INTERFACE OFFSET SIGNALING 有权
    记忆界面偏移信号

    公开(公告)号：US20140281328A1

    公开(公告)日：2014-09-18

    申请号：US13842515

    申请日：2013-03-15

    Applicant: QUALCOMM INCORPORATED

    Inventor： Shree Krishna Pandey ,  Dexter T. Chun

    IPC: G11C7/22

    CPC classification number: G11C7/227 ,  G06F1/10 ,  G06F13/1689 ,  G06F13/4243

    Abstract: A memory interface includes circuitry configured for applying a variable delay to a portion of a data signal and applying a variable delay to a data strobe. The delayed data strobe samples the delayed portion of the data signal. Delayed portions of the data signal are spaced away from non-delayed portions of the data signal by alternating the routing of delayed bits and non-delayed bits of the data signal. A training block determines and sets a value of the variable delay corresponding to a largest value of a number of recorded eye aperture widths.

    Abstract translation: 存储器接口包括经配置以将可变延迟应用于数据信号的一部分并将可变延迟应用于数据选通的电路。 延迟数据选通对数据信号的延迟部分进行采样。 通过交替数据信号的延迟位和非延迟位的路由，数据信号的延迟部分与数据信号的非延迟部分间隔开。 训练块确定并设置与记录的眼孔宽度的数量的最大值相对应的可变延迟的值。

    VERTICAL INTERCONNECTS CROSSTALK OPTIMIZATION
    20.
    发明申请
    VERTICAL INTERCONNECTS CROSSTALK OPTIMIZATION 审中-公开
    垂直互连CROSSTALK优化

    公开(公告)号：US20140252638A1

    公开(公告)日：2014-09-11

    申请号：US13935940

    申请日：2013-07-05

    Applicant: QUALCOMM Incorporated

    Inventor： Shree Krishna Pandey ,  Changyu Sun

    IPC: G06F17/50

    CPC classification number: G06F17/5036 ,  G06F17/5068 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/82 ,  G11C5/005 ,  G11C5/063

    Abstract: A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus generate a plurality of interconnect patterns for a set of vertical interconnects. Each interconnect pattern may be different from the other interconnect patterns. Each interconnect pattern may define relative locations for the set of vertical interconnects within a predefined area of a substrate in the semiconductor device. Highest crosstalk is determined for each of the interconnect patterns and the interconnect pattern with the minimum highest crosstalk is selected as a preferred pattern. One or more sets of interconnects is formed on a substrate in accordance with the preferred pattern. At least one set of interconnects may be rotated with respect to another set of interconnects on the substrate to minimize crosstalk between the sets of interconnects.

    Abstract translation: 提供了一种用于无线通信的方法，装置和计算机程序产品。 该装置为一组垂直互连产生多个互连图案。 每个互连图案可以不同于其他互连图案。 每个互连图案可以限定半导体器件中的衬底的预定区域内的垂直互连组的相对位置。 对于每个互连图案确定最高串扰，并且选择具有最小最高串扰的互连图案作为优选图案。 根据优选图案在基板上形成一组或多组互连。 至少一组互连可以相对于衬底上的另一组互连旋转，以最小化互连组之间的串扰。

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