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    LOW-POWER CLOCKING FOR A HIGH-SPEED MEMORY INTERFACE
    14.
    发明申请
    LOW-POWER CLOCKING FOR A HIGH-SPEED MEMORY INTERFACE 审中-公开
    用于高速存储器接口的低功耗时钟

    公开(公告)号：US20170017587A1

    公开(公告)日：2017-01-19

    申请号：US15204755

    申请日：2016-07-07

    Applicant: QUALCOMM Incorporated

    Inventor： David West ,  Vaishnav Srinivas ,  Michael Brunolli ,  Jungwon Suh

    IPC: G06F13/16 ,  G11C7/22 ,  G06F13/40 ,  H03L7/08

    CPC classification number: G06F13/1689 ,  G06F13/4068 ,  G06F2213/0038 ,  G11C7/222 ,  H03L7/0807 ,  Y02D10/14 ,  Y02D10/151

    Abstract: Methods, apparatus, and system for use in adaptive communication interfaces are disclosed. An adaptive communication interface is provided, in which a high-speed clock provided in a high-speed mode of operation is suppressed in a low-power mode of operation. In the low-power mode of operation, a low-speed command dock is used for data transfers between a memory device and a system-on-chip, applications processor or other device. A method for operating the adaptive communication interface may include using a first clock signal to control transmissions of commands to a memory device over a command bus. In a first mode of operation, the first clock signal controls data transmissions over the adaptive communication interface. In a second mode of operation, the second clock signal controls data transmissions over the adaptive communication interface. The frequency of the second clock signal may be greater than the frequency of the first clock signal.

    Abstract translation: 公开了在自适应通信接口中使用的方法，装置和系统。 提供了一种自适应通信接口，其中在低功率操作模式中抑制了以高速操作模式提供的高速时钟。 在低功耗操作模式下，低速指令基座用于存储器件与片上系统，应用处理器或其他器件之间的数据传输。 用于操作自适应通信接口的方法可以包括使用第一时钟信号来通过命令总线控制对存储器设备的命令的传输。 在第一操作模式中，第一时钟信号控制通过自适应通信接口的数据传输。 在第二种操作模式中，第二时钟信号通过自适应通信接口控制数据传输。 第二时钟信号的频率可以大于第一时钟信号的频率。

    DELAY CIRCUIT
    15.
    发明申请
    DELAY CIRCUIT 有权
    延时电路

    公开(公告)号：US20160079971A1

    公开(公告)日：2016-03-17

    申请号：US14489055

    申请日：2014-09-17

    Applicant: QUALCOMM Incorporated

    Inventor： Guneet Singh ,  Yuehchun Claire Cheng ,  Jan Christian Diffenderfer ,  Vaishnav Srinivas ,  Robert Won Chol Kim

    IPC: H03K5/13

    CPC classification number: H03K5/13 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4076 ,  G11C29/023 ,  G11C29/028 ,  H03K2005/00019

    Abstract: Systems and methods for delay control are described herein. In one embodiment, a delay circuit comprises a first delay path and a second delay path. The delay circuit also comprises a plurality of switches, wherein each switch is coupled between different points on the first and second delay paths, and each switch is configured to turn on or off in response to a respective one of a plurality of select signals. The delay circuit further comprises a multiplexer having a first input coupled to an output of the first delay path, a second input coupled to an output of the second delay path, and an output coupled to an output of the delay circuit, wherein the multiplexer is configured to selectively couple one of the outputs of the first and second delay paths to the output of the delay circuit in response to a second select signal.

    Abstract translation: 本文描述了用于延迟控制的系统和方法。 在一个实施例中，延迟电路包括第一延迟路径和第二延迟路径。 延迟电路还包括多个开关，其中每个开关耦合在第一和第二延迟路径上的不同点之间，并且每个开关被配置为响应于多个选择信号中的相应一个而导通或关断。 延迟电路还包括多路复用器，其具有耦合到第一延迟路径的输出的第一输入，耦合到第二延迟路径的输出的第二输入和耦合到延迟电路的输出的输出，其中多路复用器是 被配置为响应于第二选择信号选择性地将第一和第二延迟路径的输出之一耦合到延迟电路的输出。

    Integrated circuit floorplan for compact clock distribution
    16.
    发明授权
    Integrated circuit floorplan for compact clock distribution 有权
    集成电路平面图，实现紧凑的时钟分配

    公开(公告)号：US09032358B2

    公开(公告)日：2015-05-12

    申请号：US13787647

    申请日：2013-03-06

    Applicant: QUALCOMM Incorporated

    Inventor： Vaishnav Srinivas ,  Robert Won Chol Kim ,  Philip Michael Clovis ,  David Ian West

    IPC: G06F17/50 ,  H01L27/02

    CPC classification number: H01L27/0207 ,  G06F17/5072 ,  G06F2217/40

    Abstract: An integrated circuit includes core logic and a plurality of interface blocks disposed about a periphery of the core logic. A plurality of input or output (I/O) circuits is assigned to one of the plurality of interface blocks. The I/O circuits include external I/O circuits coupled to a device other than the integrated circuit and internal I/O circuits coupled to the integrated circuit. Each interface block includes a first plurality of I/O circuits disposed on a first side of the interface block and a second plurality of I/O circuits disposed on a second side of the interface block. Each interface block also includes interface logic for the interface block between the first plurality of I/O circuits and the second plurality of I/O circuits, and a logic hub that includes a clock distribution of minimal length that drives launch logic and capture logic to form the I/O circuits of the interface block.

    Abstract translation: 集成电路包括核心逻辑和围绕核心逻辑的外围设置的多个接口块。 多个输入或输出（I / O）电路被分配给多个接口块中的一个。 I / O电路包括耦合到集成电路以外的器件的外部I / O电路和耦合到集成电路的内部I / O电路。 每个接口块包括设置在接口块的第一侧上的第一多个I / O电路和设置在接口块的第二侧上的第二多个I / O电路。 每个接口块还包括用于在第一多个I / O电路和第二多个I / O电路之间的接口块的接口逻辑，以及逻辑集线器，其包括驱动启动逻辑和捕获逻辑的最小长度的时钟分配 形成接口块的I / O电路。

    Measure-based delay circuit
    17.
    发明授权
    Measure-based delay circuit 有权
    基于测量的延迟电路

    公开(公告)号：US08957714B2

    公开(公告)日：2015-02-17

    申请号：US13831201

    申请日：2013-03-14

    Applicant: QUALCOMM Incorporated

    Inventor： Vaishnav Srinivas ,  Jan Christian Diffenderfer ,  Philip Michael Clovis ,  David Ian West

    IPC: H03L7/00 ,  H03K5/159

    CPC classification number: H03K5/159

    Abstract: A master measure circuit is disclosed that may select from various nodes on a delay path carrying a signal. The master measure circuit measures the delay for propagation of the signal from one selected node to another selected node and controls an adjustable delay circuit in the delay path accordingly.

    Abstract translation: 公开了可以在承载信号的延迟路径上的各个节点进行选择的主测量电路。 主测量电路测量信号从一个选定节点传播到另一个选定节点的延迟，并相应地控制延迟路径中的可调节延迟电路。

    INTEGRATED CIRCUIT FLOORPLAN FOR COMPACT CLOCK DISTRIBUTION
    18.
    发明申请
    INTEGRATED CIRCUIT FLOORPLAN FOR COMPACT CLOCK DISTRIBUTION 有权
    用于紧凑时钟分配的集成电路FLOORPLAN

    公开(公告)号：US20140253228A1

    公开(公告)日：2014-09-11

    申请号：US13787647

    申请日：2013-03-06

    Applicant: QUALCOMM INCORPORATED

    Inventor： Vaishnav Srinivas ,  Robert Won Chol Kim ,  Philip Michael Clovis ,  David Ian West

    IPC: H01L27/02

    CPC classification number: H01L27/0207 ,  G06F17/5072 ,  G06F2217/40

    Abstract: An integrated circuit includes core logic and a plurality of interface blocks disposed about a periphery of the core logic. A plurality of input or output (I/O) circuits is assigned to one of the plurality of interface blocks. The I/O circuits include external I/O circuits coupled to a device other than the integrated circuit and internal I/O circuits coupled to the integrated circuit. Each interface block includes a first plurality of I/O circuits disposed on a first side of the interface block and a second plurality of I/O circuits disposed on a second side of the interface block. Each interface block also includes interface logic for the interface block between the first plurality of I/O circuits and the second plurality of I/O circuits, and a logic hub that includes a clock distribution of minimal length that drives launch logic and capture logic to form the I/O circuits of the interface block.

    Abstract translation: 集成电路包括核心逻辑和围绕核心逻辑的外围设置的多个接口块。 多个输入或输出（I / O）电路被分配给多个接口块中的一个。 I / O电路包括耦合到集成电路以外的器件的外部I / O电路和耦合到集成电路的内部I / O电路。 每个接口块包括设置在接口块的第一侧上的第一多个I / O电路和设置在接口块的第二侧上的第二多个I / O电路。 每个接口块还包括用于在第一多个I / O电路和第二多个I / O电路之间的接口块的接口逻辑，以及逻辑集线器，其包括驱动启动逻辑和捕获逻辑的最小长度的时钟分配 形成接口块的I / O电路。

    METHOD AND APPARATUS FOR SELECTIVELY TERMINATING SIGNALS ON A BIDIRECTIONAL BUS BASED ON BUS SPEED
    19.
    发明申请
    METHOD AND APPARATUS FOR SELECTIVELY TERMINATING SIGNALS ON A BIDIRECTIONAL BUS BASED ON BUS SPEED 有权
    基于总线速度的双向总线上的选择性终止信号的方法和装置

    公开(公告)号：US20140253173A1

    公开(公告)日：2014-09-11

    申请号：US13787926

    申请日：2013-03-07

    Applicant: QUALCOMM INCORPORATED

    Inventor： Dexter T. Chun ,  Sumeet S. Sethi ,  John D. Eaton ,  Vinodh R. Cuppu ,  Vikram Arora ,  Vaishnav Srinivas ,  Muhammad A. Muneer ,  Isaac D. Berk

    IPC: H03K19/0175

    CPC classification number: H04L25/0278 ,  G06F13/4086 ,  H03K19/0005 ,  H03K19/017545 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A method of controlling signal termination includes providing first logic for selectively terminating signals received at a first device on a bidirectional data bus, providing second logic for selectively terminating signals received at a second device on the bidirectional data bus, sending first signals from the first device to the second device on the bidirectional data bus at a first speed, stopping the sending of the first signals, after stopping the sending of the first signals, enabling the second logic and shifting a reference voltage of the second device from a first level to a second level, after enabling the second logic at the second device, sending second signals from the first device to the second device on the bidirectional data bus at a higher speed, and controlling the first logic based on a speed of signals received at the first device on the bidirectional data bus.

    Abstract translation: 一种控制信号终止的方法包括：提供用于选择性地终止在双向数据总线上在第一设备处接收的信号的第一逻辑，提供用于选择性地终止在双向数据总线上的第二设备处接收的信号的第二逻辑，从第一设备发送第一信号 以第一速度传送到双向数据总线上的第二设备，在停止发送第一信号之后停止发送第一信号，使得第二逻辑能够使第二设备的参考电压从第一电平移位到 在第二设备启用第二逻辑之后，以更高的速度在双向数据总线上从第一设备向第二设备发送第二信号，并且基于在第一设备处接收到的信号的速度来控制第一逻辑 在双向数据总线上。

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