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    Measure-Based Delay Circuit
    1.
    发明申请
    Measure-Based Delay Circuit 有权
    基于测量的延迟电路

    公开(公告)号：US20140266357A1

    公开(公告)日：2014-09-18

    申请号：US13831201

    申请日：2013-03-14

    Applicant: QUALCOMM INCORPORATED

    Inventor： Vaishnav Srinivas ,  Jan Diffenderfer ,  Philip Michael Clovis ,  David Ian West

    IPC: H03K5/159

    CPC classification number: H03K5/159

    Abstract: A master measure circuit is disclosed that may select from various nodes on a delay path carrying a signal. The master measure circuit measures the delay for propagation of the signal from one selected node to another selected node and controls an adjustable delay circuit in the delay path accordingly.

    Abstract translation: 公开了可以在承载信号的延迟路径上的各个节点进行选择的主测量电路。 主测量电路测量信号从一个选定节点传播到另一个选定节点的延迟，并相应地控制延迟路径中的可调节延迟电路。

    CLOCK AND DATA RECOVERY WITH HIGH JITTER TOLERANCE AND FAST PHASE LOCKING
    3.
    发明申请
    CLOCK AND DATA RECOVERY WITH HIGH JITTER TOLERANCE AND FAST PHASE LOCKING 有权
    时钟和数据恢复与高耐久性和快速锁相

    公开(公告)号：US20150318978A1

    公开(公告)日：2015-11-05

    申请号：US14268850

    申请日：2014-05-02

    Applicant: QUALCOMM Incorporated

    Inventor： Yu Song ,  Jan Christian Diffenderfer ,  Nan Chen ,  David Ian West ,  Paul Lawrence Viani

    IPC: H04L7/00 ,  H03L7/091

    CPC classification number: H04L7/0016 ,  H03L7/0807 ,  H03L7/091 ,  H04L7/0083 ,  H04L7/0338

    Abstract: Systems and methods for recovering clock and data from a data input signal are disclosed that sample a plurality of clock phase signals with the data input signal to determine a timing relationship between the data input signal and the clock phase signals and use the determined to timing relationship to select one of the clock phase signals to use for sampling the data input signal to produce recovered data. The CDR can include a glitch suppression module to suppress glitches on the clock output signal that could be caused by large instantaneous jitter on the data input signal. A clock and data recovery circuit (CDR) using these methods can quickly lock to a new data input signal and can reliably receive data when there is large instantaneous timing jitter on the data input signal.

    Abstract translation: 公开了用于从数据输入信号恢复时钟和数据的系统和方法，用数据输入信号对多个时钟相位信号进行采样，以确定数据输入信号和时钟相位信号之间的定时关系，并使用确定的定时关系 选择一个时钟相位信号用于采样数据输入信号以产生恢复的数据。 CDR可以包括毛刺抑制模块，以抑制可能由数据输入信号上的大的瞬时抖动引起的时钟输出信号的毛刺。 使用这些方法的时钟和数据恢复电路（CDR）可以快速锁定到新的数据输入信号，并且可以在数据输入信号上存在大的瞬时定时抖动时可靠地接收数据。

    PROVIDING MEMORY TRAINING OF DYNAMIC RANDOM ACCESS MEMORY (DRAM) SYSTEMS USING PORT-TO-PORT LOOPBACKS, AND RELATED METHODS, SYSTEMS, AND APPARATUSES
    10.
    发明申请
    PROVIDING MEMORY TRAINING OF DYNAMIC RANDOM ACCESS MEMORY (DRAM) SYSTEMS USING PORT-TO-PORT LOOPBACKS, AND RELATED METHODS, SYSTEMS, AND APPARATUSES 有权
    使用端口到端口循环提供动态随机存取存储器（DRAM）系统的存储器训练以及相关方法，系统和装置

    公开(公告)号：US20150213849A1

    公开(公告)日：2015-07-30

    申请号：US14589145

    申请日：2015-01-05

    Applicant: QUALCOMM Incorporated

    Inventor： Vaishnav Srinivas ,  Michael Joseph Brunolli ,  Dexter Tamio Chun ,  David Ian West

    IPC: G11C7/10

    CPC classification number: G11C7/1072 ,  G11C29/022 ,  G11C29/028

    Abstract: Providing memory training of dynamic random access memory (DRAM) systems using port-to-port loopbacks, and related methods, systems, and apparatuses are disclosed. In one aspect, a first port within a DRAM system is coupled to a second port via a loopback connection. A training signal is sent to the first port from a System-on-Chip (SoC), and passed to the second port through the loopback connection. The training signal is then returned to the SoC, where it may be examined by a closed-loop training engine of the SoC. A training result corresponding to a hardware parameter may be recorded, and the process may be repeated until an optimal result for the hardware parameter is achieved at the closed-loop training engine. By using a port-to-port loopback configuration, the DRAM system parameters regarding timing, power, and other parameters associated with the DRAM system may be trained more quickly and with lower boot memory usage.

    Abstract translation: 提供使用端口到端口环回的动态随机存取存储器（DRAM）系统的存储器训练以及相关方法，系统和装置。 在一个方面，DRAM系统中的第一端口经由环回连接耦合到第二端口。 训练信号从片上系统（SoC）发送到第一个端口，并通过环回连接传递到第二个端口。 然后训练信号返回到SoC，在那里可以通过SoC的闭环训练引擎检查训练信号。 可以记录与硬件参数对应的训练结果，并且可以重复该过程，直到在闭环训练引擎上实现硬件参数的最佳结果。 通过使用端口到端口环回配置，关于与DRAM系统相关联的定时，功率和其他参数的DRAM系统参数可以被更快地训练并且具有较低的启动存储器使用。

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