公开(公告)号：US09971666B2

公开(公告)日：2018-05-15

申请号：US15060221

申请日：2016-03-03

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  James Lionel Panian ,  George Alan Wiley ,  Amit Gil

IPC: G06F3/00 ,  G06F11/00 ,  G06F11/30 ,  G06F9/44 ,  G06F15/78 ,  G06F1/32 ,  G06F15/17

CPC classification number: G06F11/3051 ,  G06F1/3209 ,  G06F1/3278 ,  G06F9/4418 ,  G06F11/3041 ,  G06F15/17 ,  G06F15/7807 ,  Y02D10/157

Abstract: System, methods, and apparatuses are described that facilitate a first device to transmit/retransmit a message to a second device. The first device transmits a first message to the second device. The first device then receives a second message and identifies a bit of the second message indicating an originator of the second message. If the bit indicates the first device as the originator of the second message, then the second message is an echo of the first message. Reception of the echo indicates that the second device is in a sleep state. Accordingly, the first device waits for the second device to wake and retransmits the first message to the second device to ensure that any packets lost during the original transmission of the first message (when the second device was asleep) are now retransmitted while the second device is known to be awake.

公开(公告)号：US09965410B2

公开(公告)日：2018-05-08

申请号：US15002558

申请日：2016-01-21

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt

IPC: G06F13/00 ,  G06F13/18 ,  H04L12/40 ,  G06F13/364 ,  G06F13/42 ,  G06F13/38 ,  H04L12/403 ,  G06F12/14

CPC classification number: G06F13/18 ,  G06F12/1425 ,  G06F13/364 ,  G06F13/385 ,  G06F13/4282 ,  H04L12/40143 ,  H04L12/40182 ,  H04L12/403

Abstract: Priority-based data communication over multiple communication buses is disclosed. In this regard, an electronic device is communicatively coupled to a first communication bus and a second communication bus. The electronic device is configured to detect communication signals communicated over the first communication bus and the second communication bus. If the communication signals are detected on both the first communication bus and the second communication bus, the electronic device is further configured to protect data received over the second communication bus from being overwritten by data received over the first communication bus. By configuring the electronic device to support multiple communication buses, it is possible to configure one of the multiple communication buses as a priority communication bus, thus allowing time-critical communications to be carried out over the priority communication bus in a timely manner without preempting ongoing communications on other communication buses.

公开(公告)号：US20180034767A1

公开(公告)日：2018-02-01

申请号：US15221973

申请日：2016-07-28

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Radu Pitigoi-Aron ,  Richard Dominic Wietfeldt

IPC: H04L29/12 ,  H04W52/02 ,  H04W72/12 ,  H04L12/40

CPC classification number: H04L61/2061 ,  G06F13/37 ,  H04L12/40013 ,  H04W52/0235 ,  H04W72/1263

Abstract: Time-sequenced multi-device address assignment is provided. In this regard, an electronic device includes a plurality of client devices that are daisy-chained to a host interface port in a host controller by a reset line. The host controller is configured to assert the reset line to reset the daisy-chained client devices and then sequentially de-assert the reset line for the daisy-chained client devices according to a determined time sequence. Accordingly, the host controller assigns a unique client device address to each of the client devices when the reset line is de-asserted for the client device. By daisy-chaining the client devices via the reset line and sequentially assigning the unique client device addresses based on the determined time sequence, it is possible to assign the unique client device addresses from a single host interface port, thus reducing design complexity, footprint, and power consumption in the electronic device.

公开(公告)号：US20170313416A1

公开(公告)日：2017-11-02

申请号：US15144105

申请日：2016-05-02

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Jose Corleto

IPC: B64C39/02 ,  B64D47/00 ,  B64D47/08 ,  B64D47/02 ,  H04N7/18 ,  G06K9/00

CPC classification number: B64C39/024 ,  B64C2201/108 ,  B64C2201/127 ,  B64C2201/146 ,  B64D47/00 ,  B64D47/02 ,  B64D47/08 ,  G03B15/006 ,  G03B15/03 ,  G03B15/05 ,  G05D1/104 ,  G06K9/0063 ,  H04N7/181

Abstract: An aerial imaging system and method of aerially capturing an image including a first unmanned aerial vehicle (UAV) and a second UAV. The first UAV includes a camera and may be configured to receive input from an operator. The second UAV may be configured to dock with and deploy from the first UAV. The second UAV includes a light configured to provide remote illumination for the camera. The light on the second UAV may be activated to illuminate a target of photography by the camera while the second UAV is flown separate from the first UAV.

公开(公告)号：US20170228327A1

公开(公告)日：2017-08-10

申请号：US15040271

申请日：2016-02-10

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Wietfeldt

IPC: G06F13/16 ,  G06F13/12 ,  G06F13/40 ,  G06F13/42 ,  G06F15/78

CPC classification number: G06F13/161 ,  G06F13/126 ,  G06F13/4018 ,  G06F13/4282 ,  G06F13/4291 ,  G06F15/7817

Abstract: A serial interface is provided with a finite state machine configured to compare a current state for a plurality of signals to a previous state to determine whether to transmit a frame including the plurality of signals or to transmit a frame that includes only a bit position of a changed one of the signals.

公开(公告)号：US20170168967A1

公开(公告)日：2017-06-15

申请号：US14965511

申请日：2015-12-10

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  Peter Shah

IPC: G06F13/24 ,  G06F13/10

CPC classification number: G06F13/24 ,  G06F13/102 ,  H03M1/785

Abstract: A host integrated circuit is provided with an interrupt aggregator having a signal terminal for coupling to the signal end of an R-2R resistor ladder that has a plurality of rungs corresponding to a plurality of peripheral devices. The interrupt aggregator is configured to process a voltage signal received at the signal terminal to identify any of the peripheral device that intend to trigger an interrupt to a processor.

公开(公告)号：US20170083467A1

公开(公告)日：2017-03-23

申请号：US14860568

申请日：2015-09-21

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt

IPC: G06F13/362 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F13/362 ,  G06F13/4068 ,  G06F13/4282 ,  G06F13/4291

Abstract: A modified serial peripheral interface (SPI) is provided in each of a master device and a plurality of slave devices that does not use a slave select line. The master device may thus engage in full-duplex serial communication with each slave device through an SPI MOSI line, an SPI MISO line, and an SPI clock line.

公开(公告)号：US20150310990A1

公开(公告)日：2015-10-29

申请号：US14261373

申请日：2014-04-24

Applicant: Qualcomm Incorporated

Inventor： Lalan Jee Mishra ,  Shree Krishna Pandey ,  Nazanin Darbanian ,  John David Eaton

IPC: H01G4/30

CPC classification number: H01G4/30 ,  H01G4/012 ,  H01G4/12 ,  H01G4/232

Abstract: Aspects of a method of manufacturing a capacitor are provided. The method includes layering a plurality of dielectric plates. The plurality of dielectric plates includes a first dielectric plate having a first conductive region and a second conductive region on a surface of the first dielectric plate. The method further includes forming an inner electrode through an axis of the layered plurality of dielectric plates. The inner electrode electrically couples to the first conductive region on the surface of the first dielectric plate. The method further includes forming an outer electrode, where the outer electrode electrically couples to the second conductive region on the surface of the first dielectric plate.

Abstract translation: 提供制造电容器的方法的方面。 该方法包括层叠多个电介质板。 多个电介质板包括在第一电介质板的表面上具有第一导电区域和第二导电区域的第一电介质板。 该方法还包括通过层叠的多个电介质板的轴线形成内部电极。 内部电极电耦合到第一电介质板的表面上的第一导电区域。 该方法还包括形成外部电极，其中外部电极电耦合到第一电介质板的表面上的第二导电区域。

公开(公告)号：US20150149672A1

公开(公告)日：2015-05-28

申请号：US14540366

申请日：2014-11-13

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  Mohit Kishore Prasad

IPC: G06F13/42 ,  G06F9/455

CPC classification number: G06F13/4221 ,  G06F9/45533 ,  G06F13/4273

Abstract: A virtual GPIO architecture for an integrated circuit is provided that both serializes virtual GPIO signals and deserializes virtual GPIO signals without the need for an external clock.

Abstract translation: 提供了一个用于集成电路的虚拟GPIO架构，既可以串行化虚拟GPIO信号，也可以反序列化虚拟GPIO信号，无需外部时钟。

公开(公告)号：US12034469B2

公开(公告)日：2024-07-09

申请号：US17127709

申请日：2020-12-18

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  Umesh Srikantiah ,  Karthik Manivannan

IPC: H04W48/18 ,  G06F13/40 ,  G06F13/42 ,  H04B1/401 ,  H04W88/06

CPC classification number: H04B1/401 ,  G06F13/4027 ,  G06F13/4291

Abstract: Systems and methods for variable stride counting for timed-triggers in a radio frequency front end (RFFE) bus modify how a master clock controls counters in slaves. In particular, instead of having the master clock change a counter at a slave device on a one-to-one clock tick-to-counter change, exemplary aspects of the present disclosure contemplate allowing a bus ownership master (BOM) to select a stride size wherein each clock tick causes the counter to change by the size of the stride. Clock ticks are then sent less frequently over the clock line of the RFFE bus. In this fashion, fewer clock ticks are required to change the counter to the trigger event.