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公开(公告)号：US12086010B2
公开(公告)日：2024-09-10
申请号：US17891768
申请日：2022-08-19
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Brian Hing-Kit Tsang , Barry William Daly
IPC: G06F1/3237 , G06F1/324 , G06F1/3287 , G06F13/16 , G06F13/28
CPC classification number: G06F1/3237 , G06F1/324 , G06F1/3287 , G06F13/1673 , G06F13/1689 , G06F13/28 , Y02D10/00 , Y02D30/50
Abstract: The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts separated by intervening low-power intervals during which portions of the interface are powered down.
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公开(公告)号：US20210064116A1
公开(公告)日：2021-03-04
申请号：US17002269
申请日：2020-08-25
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Brian Hing-Kit Tsang , Barry William Daly
IPC: G06F1/3237 , G06F13/16 , G06F1/324 , G06F1/3287 , G06F13/28
Abstract: The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts separated by intervening low-power intervals during which portions of the interface are powered down.
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公开(公告)号：US09344064B2
公开(公告)日：2016-05-17
申请号：US14808936
申请日：2015-07-24
Applicant: Rambus Inc.
Inventor： Kambiz Kaviani , Kashinath Prabhu , Brian Hing-Kit Tsang , Jared L. Zerbe
Abstract: Embodiments of an integrated circuit (IC) comprising frequency change detection circuitry are described. Some embodiments include first circuitry to generate a second clock signal based on a first clock signal, wherein the first clock signal has a first clock frequency, and wherein the second clock signal has a second clock frequency that is an integral multiple of the first clock frequency. The embodiments further include second circuitry to obtain samples by oversampling the first clock signal using the second clock signal. Additionally, the embodiments include third circuitry to detect a change in the first clock frequency based on the samples.
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公开(公告)号：US11455022B2
公开(公告)日：2022-09-27
申请号：US17002269
申请日：2020-08-25
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Brian Hing-Kit Tsang , Barry William Daly
IPC: G06F1/324 , G06F1/3237 , G06F13/16 , G06F1/3287 , G06F13/28
Abstract: The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts separated by intervening low-power intervals during which portions of the interface are powered down.
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公开(公告)号：US10788882B2
公开(公告)日：2020-09-29
申请号：US16134577
申请日：2018-09-18
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Brian Hing-Kit Tsang , Barry William Daly
IPC: G06F1/3203 , G06F1/3237 , G06F13/16 , G06F1/324 , G06F1/3287 , G06F13/28
Abstract: The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts separated by intervening low-power intervals during which portions of the interface are powered down.
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Patent Agency Ranking
公开(公告)号：US10108246B2
公开(公告)日：2018-10-23
申请号：US15390367
申请日：2016-12-23
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Brian Hing-Kit Tsang , Barry William Daly
Abstract: The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts separated by intervening low-power intervals during which portions of the interface are powered down.
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17.发明申请公开(公告)号：US20180175837A1
公开(公告)日：2018-06-21
申请号：US15823226
申请日：2017-11-27
Applicant: Rambus Inc.
Inventor： Brian Hing-Kit Tsang , Jared L. Zerbe
IPC: H03K5/133 , G06F13/16 , G11C7/10 , G11C7/22 , H03K7/06 , H03K3/03 , G11C8/18 , H03L7/00 , G11C11/16 , H01L43/08 , H03K5/00 , G11C11/15
CPC classification number: H03K5/133 , G06F13/1689 , G11C7/10 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/15 , G11C11/16 , H01L43/08 , H03K3/0315 , H03K7/06 , H03K2005/00019 , H03L7/00 , Y02D10/14
Abstract: Methods and apparatuses for communicating information are described. In some embodiments, a first integrated circuit (IC) provides a clock signal and a data signal to a second IC, wherein the data bits of the data signal are timed according to the clock signal, and wherein the frequency of the clock signal is capable of being changed even when the data signal is valid.
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18.发明授权公开(公告)号：US09893720B2
公开(公告)日：2018-02-13
申请号：US15015917
申请日：2016-02-04
Applicant: Rambus Inc.
Inventor： Brian Hing-Kit Tsang , Jared L. Zerbe
IPC: G11C11/16 , H03K5/133 , G11C8/18 , H03L7/00 , G11C7/10 , G11C7/22 , G06F13/16 , H03K3/03 , H03K7/06 , H01L43/08 , G11C11/15 , H03K5/00
CPC classification number: H03K5/133 , G06F13/1689 , G11C7/10 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/15 , G11C11/16 , H01L43/08 , H03K3/0315 , H03K7/06 , H03K2005/00019 , H03L7/00 , Y02D10/14
Abstract: Methods and apparatuses for communicating information are described. In some embodiments, a first integrated circuit (IC) provides a clock signal and a data signal to a second IC, wherein the data bits of the data signal are timed according to the clock signal, and wherein the frequency of the clock signal is capable of being changed even when the data signal is valid.
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公开(公告)号：US20170205871A1
公开(公告)日：2017-07-20
申请号：US15390367
申请日：2016-12-23
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Brian Hing-Kit Tsang , Barry William Daly
CPC classification number: G06F1/3237 , G06F1/324 , G06F1/3287 , G06F13/1673 , G06F13/1689 , G06F13/28 , Y02D10/126 , Y02D10/171 , Y02D50/20
Abstract: The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts separated by intervening low-power intervals during which portions of the interface are powered down.
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公开(公告)号：US09568980B2
公开(公告)日：2017-02-14
申请号：US14416088
申请日：2013-09-06
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Brian Hing-Kit Tsang , Barry William Daly
CPC classification number: G06F1/3237 , G06F1/324 , G06F1/3287 , G06F13/1673 , G06F13/1689 , G06F13/28 , Y02D10/126 , Y02D10/171 , Y02D50/20
Abstract: The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts separated by intervening low-power intervals during which portions of the interface are powered down.
Abstract translation: 所公开的实施例涉及支持动态突发以促进存储器控制器和存储器设备之间的频率敏捷通信的系统。 在操作期间，系统监视在存储器件和存储器控制器之间的接口处接收到的参考时钟信号。 在检测到从全速率到子速率的参考时钟信号中的频率变化时，接口以突发模式操作，其中数据通过由接口的部分断电的中间的低功率间隔分开的脉冲串传送。
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