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11.发明申请公开(公告)号：US20250142228A1
公开(公告)日：2025-05-01
申请号：US18915626
申请日：2024-10-15
Applicant: Renesas Electronics Corporation
Inventor： Fukashi MORISHITA
Abstract: A semiconductor device according to this disclosure includes: a comparator circuit; a counter circuit; and a latch circuit that stores a count value of the counter circuit at a timing when an output signal of the comparator circuit changes, the counter circuit includes: a multiphase signal generator; and a plurality of flip-flop circuits including a first-stage flip-flop and second-stage and subsequent flip-flops, the first-stage flip-flop takes in an inverted signal of an output signal of a flip-flop in a final stage and each of the second-stage and subsequent flip-flops takes in an output signal of a flip-flop in a preceding stage in synchronization with each of the plurality of clock signals, and an output signal of each of the plurality of flip-flop circuits is output as a count signal of the count value.
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公开(公告)号：US20230022468A1
公开(公告)日：2023-01-26
申请号：US17850264
申请日：2022-06-27
Applicant: Renesas Electronics Corporation.
Inventor： Fukashi MORISHITA
Abstract: An image sensor including an ADC circuit receiving pixel data to be supplied in parallel from the a pixel array, outputting a reference signal in accordance with a digital code, comparing the reference signal and the pixel data, and outputting the digital code at which the reference signal and the pixel data have a predetermined relation, the ADC circuit including a ramp-signal generating circuit outputting a ramp signal having a gradient with respect to change of the digital code, the gradient being different between when the digital code is in a first range and when the digital code is in a second range different from the first range and an attenuator receiving the ramp signal to be supplied and outputting the reference signal having a gradient being the same between when the digital code is in the first range and when the digital code is in the second range.
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公开(公告)号：US20180152656A1
公开(公告)日：2018-05-31
申请号：US15797085
申请日：2017-10-30
Applicant: Renesas Electronics Corporation
Inventor： Osamu MATSUMOTO , Fukashi MORISHITA
CPC classification number: H04N5/378 , H03M1/123 , H03M1/46 , H03M1/466 , H03M1/682 , H03M1/765 , H04N5/37455
Abstract: Provided is a solid-state imaging device capable of increasing the speed of an A/D converter. The solid-state imaging device includes a successive approximation A/D converter that performs A/D conversion on an analog pixel signal. The successive approximation A/D converter includes a D/A converter, a comparator, and a successive approximation register. The D/A converter converts a digital reference signal to an analog reference signal. The successive approximation register operates based on the result of comparison by the comparator to generate the digital reference signal in such a manner that the analog reference signal approximates the analog pixel signal. The D/A converter includes a split capacitor, first capacitors, second capacitors, a switch array, a third capacitor, and a multiplexer. The first capacitors each have a first electrode coupled to the output node. The second capacitors are coupled to a second electrode of the split capacitor. The switch array is coupled to a second electrode of each of the first and second capacitors and is adapted to generate the analog reference signal at the output node by selectively applying a first reference voltage. The third capacitor is coupled to the second electrode of the split capacitor. The multiplexer is coupled to a second electrode of the third capacitor and is adapted to generate the analog reference signal at the output node by selectively applying a second reference voltage.
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公开(公告)号：US20160212367A1
公开(公告)日：2016-07-21
申请号：US15082913
申请日：2016-03-28
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Hiroto UTSUNOMIYA , Katsumi DOSAKA , Hiroshi KATO , Fukashi MORISHITA , Fumiyasu SASAKI
IPC: H04N5/3745 , H04N5/376 , H03M1/66 , H04N5/378
CPC classification number: H04N5/37455 , H03M1/1205 , H03M1/144 , H03M1/403 , H03M1/66 , H03M2201/16 , H04N5/374 , H04N5/3742 , H04N5/3765 , H04N5/378
Abstract: There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.
Abstract translation: 提供了包括可以在有限空间中布置的ADC的固态图像拾取装置。 通过垂直读出线输出的像素信号的电位被保持在节点处。 多个电容器电容耦合到保持像素信号的节点。 通过晶体管的控制，通过依次切换电容器对置电极的电压，逐步降低节点的电位。 比较器将节点的电位与像素的暗状态的电位进行比较，并且当节点的电位变得低于黑暗状态的电位时，确定数字值的高位。 此后，开始数字值的低位的转换。 因此，可以简化每个ADC的配置，并将每个ADC排列在有限的空间内。
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公开(公告)号：US20150304578A1
公开(公告)日：2015-10-22
申请号：US14689913
申请日：2015-04-17
Applicant: Renesas Electronics Corporation
Inventor： Shunsuke OKURA , Fukashi MORISHITA
CPC classification number: H04N5/378 , H04N5/363 , H04N5/374 , H04N5/3765
Abstract: The present invention provides a technique for achieving higher picture quality of a captured image by reducing noise which occurs at the time of resetting in a solid-state image sensing device and the like. A pixel array in a solid-state image sensing device includes a plurality of pixels and includes an OB pixel region and an effective pixel region. The solid-state image sensing device has a signal processing unit outputting a pixel signal of each of the pixels in the effective pixel region on the basis of the signal level of a signal output from each of the pixels. The solid-state image sensing device obtains a signal without applying a reset signal to each of the pixels in the OB pixel region, obtains the difference between the signal and a signal of a pixel in the effective pixel region, and outputs an image signal.
Abstract translation: 本发明提供了一种通过减少在固态图像感测装置等中复位时发生的噪声来获得拍摄图像的更高图像质量的技术。 固态图像感测装置中的像素阵列包括多个像素，并且包括OB像素区域和有效像素区域。 固态图像感测装置具有信号处理单元，其基于从每个像素输出的信号的信号电平，输出有效像素区域中的每个像素的像素信号。 固态图像感测装置获取信号而不对OB像素区域中的每个像素施加复位信号，获得有效像素区域中的信号与像素的信号之间的差，并输出图像信号。
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Patent Agency Ranking
公开(公告)号：US20140362273A1
公开(公告)日：2014-12-11
申请号：US14301120
申请日：2014-06-10
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Shunsuke OKURA , Fukashi MORISHITA
IPC: H04N5/3745 , H04N5/374
CPC classification number: H03M1/468 , H03M1/38 , H03M1/46 , H03M1/804 , H04N5/374 , H04N5/37455 , H04N5/378
Abstract: The present invention provides a small-sized inexpensive solid-state imaging apparatus. A D/A converter included in a successive comparison type A/D converter of the solid-state imaging apparatus includes a multiplexer which selects any of reference voltages VR0 to VR16 and sets it as an analog reference signal when coarse A/D conversion is performed, and which selects reference voltages VR (n−1) to VR (n+2) of the reference voltages VR0 to VR16 when fine A/C conversion is performed, and a capacitor array which generates an analog reference signal, based on the reference voltages VR (n−1) to VR (n+2) when the fine A/D conversion is performed. It is thus possible to reduce settling errors in reference voltage without using redundant capacitors.
Abstract translation: 本发明提供一种小型便宜的固态成像装置。 包括在固态成像装置的连续比较型A / D转换器中的AD / A转换器包括多路复用器，其选择参考电压VR0至VR16中的任何一个，并且当执行粗略A / D转换时将其设置为模拟参考信号， 并且当执行精细的A / C转换时，其选择参考电压VR0至VR16的参考电压VR（n-1）至VR（n + 2），以及基于参考电压产生模拟参考信号的电容器阵列 当进行精细的A / D转换时，VR（n-1）至VR（n + 2）。 因此，可以在不使用冗余电容器的情况下降低参考电压的稳定误差。
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公开(公告)号：US20130249624A1
公开(公告)日：2013-09-26
申请号：US13900210
申请日：2013-05-22
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Mihoko AKIYAMA , Futoshi IGAUE , Kenji YOSHINAGA , Masashi MATSUMURA , Fukashi MORISHITA
IPC: G05F1/46
Abstract: A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.
Abstract translation: 半导体集成电路器件具有设置在每个用于六个存储器宏的电源电路单元的负电压产生电路。 因此，相对于负电压的变化的响应增加。 在待机模式下，通过开关电路连接六个存储器宏的负电压供给线，并且仅在六个电源电路单元的六个负电压产生电路中仅一个电源电路单元的负电压产生电路 活性。 因此，可以防止待机电流的增加。
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公开(公告)号：US20240267068A1
公开(公告)日：2024-08-08
申请号：US18397714
申请日：2023-12-27
Applicant: Renesas Electronics Corporation
Inventor： Wataru SAITO , Fukashi MORISHITA
CPC classification number: H04B1/1027 , H04B1/40
Abstract: The circuit area of the semiconductor device in which the transmission period and the reception period are alternately repeated is reduced. The semiconductor device includes a transmission circuit and a receiving circuit. The receiving circuit includes a gain control circuit that samples the input signal to adjust the gain of the receiving circuit during the reception period and adjusts the gain based on the sampling result during the transmission period.
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公开(公告)号：US20240171835A1
公开(公告)日：2024-05-23
申请号：US18498278
申请日：2023-10-31
Applicant: Renesas Electronics Corporation
Inventor： Wataru SAITO , Fukashi MORISHITA
CPC classification number: H04N23/52 , H04N23/6812 , H04N23/687
Abstract: A programmable gain amplifier provided in a semiconductor device includes a fully differential amplifier configured to amplify differential input voltages having an offset voltage. First and second correction voltages are input to a non-inverting input node and an inverting input node of the fully differential amplifier via first and second resistance elements, respectively.
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公开(公告)号：US20240151804A1
公开(公告)日：2024-05-09
申请号：US18482137
申请日：2023-10-06
Applicant: Renesas Electronics Corporation
Inventor： Norihito KATOU , Fukashi MORISHITA
IPC: G01S5/02
CPC classification number: G01S5/0205
Abstract: A circuit including a first circuit, a second circuit and a controller is provided, the first circuit and the second circuit each including a sample-and-hold circuit configured to hold a level of an input signal of a specific timing and an analog-to-digital converter circuit configured to convert the level of the input signal held in the sample-and-hold circuit into digital data and to output the digital data, the controller being configured to cause the first circuit to output the level of the input signal of a first timing and to cause the second circuit to output the level of the input signal of a second timing.
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