公开(公告)号：US20170278854A1

公开(公告)日：2017-09-28

申请号：US15468673

申请日：2017-03-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichiro ABE ,  Masaaki SHINOHARA

IPC: H01L27/1157 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L27/1157 ,  H01L27/11573 ,  H01L29/66833 ,  H01L29/792

Abstract: In a MONOS memory, withstand voltage is increased between a control gate electrode over an ONO film having a charge accumulating part and a semiconductor substrate. When a silicon film is processed to form a control gate electrode, dry etching is performed for a relatively long time, thereby a recess is formed in a sidewall of the control gate electrode. Subsequently, the control gate electrode is subjected to dry oxidation treatment to form an insulating film on the sidewall of the control gate electrode including the recess, thereby an end of the bottom of the control gate electrode is separated from an end of the top of the ONO film.

公开(公告)号：US20170243750A1

公开(公告)日：2017-08-24

申请号：US15592279

申请日：2017-05-11

Applicant: Renesas Electronics Corporation

Inventor： Masaaki SHINOHARA

IPC: H01L21/28 ,  H01L27/11573 ,  H01L21/321 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H01L27/1157 ,  H01L27/11575

Abstract: Provided is a semiconductor device having improved performance. In a semiconductor substrate located in a memory cell region, a memory cell of a nonvolatile memory is formed while, in the semiconductor substrate located in a peripheral circuit region, a MISFET is formed. At this time, over the semiconductor substrate located in the memory cell region, a control gate electrode and a memory gate electrode each for the memory cell are formed first. Then, an insulating film is formed so as to cover the control gate electrode and the memory gate electrode. Subsequently, the upper surface of the insulating film is polished to be planarized. Thereafter, a conductive film for the gate electrode of the MISFET is formed and then patterned to form a gate electrode or a dummy gate electrode for the MISFET in the peripheral circuit region.

公开(公告)号：US20170221917A1

公开(公告)日：2017-08-03

申请号：US15412465

申请日：2017-01-23

Applicant: Renesas Electronics Corporation

Inventor： Masaaki SHINOHARA

IPC: H01L27/11568 ,  H01L21/311 ,  H01L21/266 ,  H01L21/265 ,  H01L29/66 ,  H01L21/02 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L27/11573 ,  H01L21/28 ,  H01L29/792 ,  H01L29/423 ,  G11C16/04 ,  H01L21/8234

CPC classification number: H01L27/11568 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823468 ,  H01L27/088 ,  H01L27/0922 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66833 ,  H01L29/792

Abstract: Deterioration in reliability is prevented regarding a semiconductor device. The deterioration is caused when an insulating film for formation of a sidewall is embedded between gate electrodes at the time of forming sidewalls having two kinds of different widths on a substrate. A sidewall-shaped silicon oxide film is formed over each sidewall of a gate electrode of a low breakdown voltage MISFET and a pattern including a control gate electrode and a memory gate electrode. Then, a silicon oxide film beside the gate electrode is removed, and a silicon oxide film is formed on a semiconductor substrate, and then etchback is performed. Accordingly, a sidewall, formed of a silicon nitride film and the silicon oxide film, is formed beside the gate electrode, and a sidewall, formed of the silicon nitride film and the silicon oxide films, is formed beside the pattern.

公开(公告)号：US20170047338A1

公开(公告)日：2017-02-16

申请号：US15180484

申请日：2016-06-13

Applicant: Renesas Electronics Corporation

Inventor： Masaaki SHINOHARA ,  Shigeo TOKUMITSU

IPC: H01L27/115 ,  H01L21/764 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8249

CPC classification number: H01L21/764 ,  H01L21/3083 ,  H01L21/31144 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7835

Abstract: A method of manufacturing a semiconductor device includes the steps of forming a plurality of gate electrodes, forming a first insulating film over the plurality of gate electrodes such that the first insulating film is embedded in a space between the plurality of gate electrodes, forming a second insulating film over the first insulating film, forming a third insulating film over the second insulating film, forming a photosensitive pattern over the third insulating film, performing etching using the photosensitive pattern as a mask to form a trench extending through the first to third insulating films and reaching a semiconductor substrate, removing the photosensitive pattern, performing etching using the exposed third insulating film as a mask to extend the trench in the semiconductor substrate, removing the third and second insulating films, and forming a fourth insulating film in the trench and over the first insulating film.

Abstract translation: 一种制造半导体器件的方法包括以下步骤：形成多个栅电极，在多个栅电极上形成第一绝缘膜，使得第一绝缘膜嵌入在多个栅电极之间的空间中，形成第二绝缘膜 在所述第一绝缘膜上形成绝缘膜，在所述第二绝缘膜上形成第三绝缘膜，在所述第三绝缘膜上形成感光图案，使用所述感光图案作为掩模进行蚀刻，以形成延伸穿过所述第一至第三绝缘膜的沟槽 并且到达半导体衬底，去除光敏图案，使用暴露的第三绝缘膜作为掩模进行蚀刻，以延伸半导体衬底中的沟槽，去除第三和第二绝缘膜，并在沟槽中形成第四绝缘膜 第一绝缘膜。

公开(公告)号：US20160181246A1

公开(公告)日：2016-06-23

申请号：US15053551

申请日：2016-02-25

Applicant: Renesas Electronics Corporation

Inventor： Masaaki SHINOHARA ,  Satoshi IIDA

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/76224 ,  H01L21/308 ,  H01L21/76205 ,  H01L21/823878 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/4916 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7833

Abstract: Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film.The invention provides a method of manufacturing a semiconductor integrated circuit device including forming a hard mask film, an opening therein, and a sidewall insulating film on the side surface thereof; forming a shallow trench in the opening with the hard mask film as a mask and oxidizing at least an exposed portion; filling the trench with an insulating film and then removing it so as to leave it outside the trench in the opening and thereby forming a drain offset STI insulating film inside and outside the trench; and forming a gate electrode extending from the upper portion of a gate insulating film in an active region contiguous thereto to the upper portion of the drain offset insulating film.

公开(公告)号：US20160086961A1

公开(公告)日：2016-03-24

申请号：US14860700

申请日：2015-09-21

Applicant: Renesas Electronics Corporation

Inventor： Fukuo OWADA ,  Masaaki SHINOHARA ,  Takahiro MARUYAMA

IPC: H01L27/115

CPC classification number: H01L27/11546 ,  H01L27/11529

Abstract: An improvement is achieved in the performance of a semiconductor device. Over a first insulating film formed over a main surface of a semiconductor substrate located in a memory formation region and having an internal charge storage portion and over a second insulating film formed over the main surface of the semiconductor substrate located in a main circuit formation region, a conductive film is formed. Then, in the memory formation region, the conductive film and the first insulating film are patterned to form a first gate electrode and a first gate insulating film while, in the main circuit formation region, the conductive film and the second insulating film are left. Then, in the main circuit formation region, the conductive film and the second insulating film are patterned to form a second gate electrode and a second gate insulating film.

Abstract translation: 在半导体器件的性能方面实现了改进。 在位于存储器形成区域中的具有内部电荷存储部分的半导体衬底的主表面上形成的第一绝缘膜上，以及形成在位于主电路形成区域中的半导体衬底的主表面上的第二绝缘膜之上， 形成导电膜。 然后，在存储器形成区域中，对导电膜和第一绝缘膜进行构图以形成第一栅电极和第一栅极绝缘膜，同时在主电路形成区域中留下导电膜和第二绝缘膜。 然后，在主电路形成区域中，对导电膜和第二绝缘膜进行构图以形成第二栅极电极和第二栅极绝缘膜。

公开(公告)号：US20200066757A1

公开(公告)日：2020-02-27

申请号：US16670918

申请日：2019-10-31

Applicant: Renesas Electronics Corporation

Inventor： Takaaki TSUNOMURA ,  Yoshiki YAMAMOTO ,  Masaaki SHINOHARA ,  Toshiaki IWAMATSU ,  Hidekazu ODA

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/78

Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.

公开(公告)号：US20180019260A1

公开(公告)日：2018-01-18

申请号：US15695410

申请日：2017-09-05

Applicant: Renesas Electronics Corporation

Inventor： Takaaki TSUNOMURA ,  Yoshiki YAMAMOTO ,  Masaaki SHINOHARA ,  Toshiaki IWAMATSU ,  Hidekazu ODA

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/417

CPC classification number: H01L27/1203 ,  H01L21/823418 ,  H01L21/823814 ,  H01L27/1207 ,  H01L29/41783 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/7834

Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.

公开(公告)号：US20170278750A1

公开(公告)日：2017-09-28

申请号：US15424798

申请日：2017-02-04

Applicant: Renesas Electronics Corporation

Inventor： Masaaki SHINOHARA

IPC: H01L21/768 ,  H01L21/265 ,  H01L27/11568 ,  H01L21/28 ,  H01L27/11573 ,  H01L29/66 ,  H01L21/266

CPC classification number: H01L21/76895 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/28282 ,  H01L21/76805 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823487 ,  H01L27/088 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66833

Abstract: When a MISFET is formed by using a gate last process and replacing dummy gate electrodes with metal gate electrodes, both of respective cap insulating films and an interlayer insulating film over a control gate electrode and the dummy gate electrodes are polished to prevent excessive polishing of the upper surface of the interlayer insulating film and the occurrence of dishing. In the gate last process, the interlayer insulating film is formed to cover the control gate electrode and the dummy gate electrodes as well as the cap insulating films located thereover. After the upper surface of the interlayer insulating is polished to expose the cap insulating films from the interlayer insulating films, etching is performed to selectively remove the cap insulating films. Subsequently, the upper surfaces of the interlayer insulating films are polished.

公开(公告)号：US20170243955A1

公开(公告)日：2017-08-24

申请号：US15409947

申请日：2017-01-19

Applicant: Renesas Electronics Corporation

Inventor： Masaaki SHINOHARA

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/06 ,  H01L27/11568 ,  H01L21/02 ,  H01L21/306 ,  H01L27/11521 ,  H01L21/033 ,  H01L21/311

Abstract: Provided is a stable manufacturing method for a semiconductor device. In the manufacturing method for a semiconductor device, first, fins with an equal width are formed in each of a memory cell portion and a logic portion of a semiconductor substrate. Then, the fins in the logic portion are etched with the fins in the memory cell covered with a mask film, thereby fabricating fins in the logic portion, each of which is narrower than the fin formed in the memory cell portion.