公开(公告)号：US10317769B2

公开(公告)日：2019-06-11

申请号：US15965900

申请日：2018-04-28

Applicant: Renesas Electronics Corporation

Inventor： Shinichi Watanuki ,  Yasutaka Nakashiba ,  Masaru Wakabayashi

IPC: G02F1/225 ,  G02F1/21

Abstract: In a semiconductor device connected to a first optical waveguide, a phase modulation unit, and a second optical waveguide in this order and having an optical modulator guiding light in a first direction, the phase modulation unit includes: a semiconductor layer whose length in the first direction is larger than a width in a second direction orthogonal to the first direction and which is made of monocrystalline silicon; a core part serving as an optical waveguide region formed on the semiconductor layer, and extending in the first direction; a pair of slab parts arranged on both sides of the core part in the second direction; a first electrode coupled with one of the slab parts; and a second electrode coupled with the other of the slab parts. The core part has a p type semiconductor region and an n type semiconductor region extending in the first direction, and the second direction coincides with a crystal orientation of the semiconductor layer.

公开(公告)号：US10295743B2

公开(公告)日：2019-05-21

申请号：US14827779

申请日：2015-08-17

Applicant: Renesas Electronics Corporation

Inventor： Hiroyuki Kunishima ,  Yasutaka Nakashiba ,  Masaru Wakabayashi ,  Shinichi Watanuki ,  Ken Ozawa ,  Tatsuya Usami ,  Yoshiaki Yamamoto ,  Keiji Sakamoto

IPC: G02B6/12 ,  G02B6/125 ,  G02B6/136

Abstract: Disclosed is an optical semiconductor device which can be improved in light shift precision and restrained from undergoing a loss in light transmission. In this device, an inner side-surface of a first optical coupling portion of an optical coupling region and an inner side-surface of a second optical coupling portion of the region are increased in line edge roughness. This manner makes light coupling ease from a first to second optical waveguide. By contrast, the following are decreased in line edge roughness: an outer side-surface of the first optical coupling portion of the optical coupling region; an outer side-surface of the second optical coupling portion of the region; two opposed side-surfaces of a portion of the first optical waveguide, the portion being any portion other than the region; and two opposed side-surfaces of a portion of the second optical waveguide, the portion being any portion other than the region.

公开(公告)号：US10026689B2

公开(公告)日：2018-07-17

申请号：US15186734

申请日：2016-06-20

Applicant: Renesas Electronics Corporation

Inventor： Teruhiro Kuwajima ,  Akira Matsumoto ,  Yasutaka Nakashiba ,  Takashi Iwadare

IPC: H01L27/08 ,  H01L23/522 ,  H01L23/495

Abstract: A SOP has a semiconductor chip. The chip includes a pair of a lower layer coil and an upper layer coil laminated through an interlayer insulating film formed therebetween, a first circuit unit electrically coupled to the upper layer coil, and a plurality of electrode pads. Further, it has a wire for electrically coupling the upper layer coil and the first circuit unit, a plurality of inner leads and outer leads arranged around the semiconductor chip, a plurality of wires for electrically coupling the electrode pads of the semiconductor chip and the inner leads, and a resin made sealing member for covering the semiconductor chip. The wire extends along the extending direction of the wires.

公开(公告)号：US09606012B2

公开(公告)日：2017-03-28

申请号：US14244820

申请日：2014-04-03

Applicant: Renesas Electronics Corporation

Inventor： Yutaka Akiyama ,  Yasutaka Nakashiba

IPC: H01L29/84 ,  G01L9/00 ,  H01L41/113

CPC classification number: G01L9/005 ,  G01L9/0055 ,  H01L29/84 ,  H01L41/113

Abstract: An object of the present invention is to suppress an error in the value detected by a pressure sensor, which may be caused when environmental temperature varies. A semiconductor substrate has a first conductivity type. A semiconductor layer is formed over a first surface of the semiconductor substrate. Each of resistance parts has a second conductivity type, and is formed in the semiconductor layer. The resistance parts are spaced apart from each other. A separation region is a region of the first conductivity type formed in the semiconductor layer, and electrically separates the resistance parts from each other. A depressed portion is formed in a second surface of the semiconductor substrate, and overlaps the resistance parts, when viewed planarly. The semiconductor layer is an epitaxial layer.

公开(公告)号：US20160203394A1

公开(公告)日：2016-07-14

申请号：US15080261

申请日：2016-03-24

Applicant: Renesas Electronics Corporation

Inventor： Yasutaka Nakashiba ,  Hiroaki Ohkubo ,  Mitsuji Okada ,  Shigeharu Nakata ,  Shuuichi Kagawa

IPC: G06K19/073 ,  H03K19/0175

CPC classification number: G06K19/073 ,  G11C7/24 ,  H03K19/017509

Abstract: A memory card includes a memory that stores data, a driver that transmits the data received from the memory, and at least one transmitter that transmits the data received from the driver to a receiver provided in an external main unit. The driver and the transmitter are provided in a single IC (Integrated Circuit) chip and are not overlapped with each other in planar view, and the transmitter includes a coil

Abstract translation: 存储卡包括存储数据的存储器，发送从存储器接收的数据的驱动器以及将从驱动器接收的数据发送到设置在外部主单元中的接收器的至少一个发送器。 驱动器和发送器设置在单个IC（集成电路）芯片中，并且在平面图中不彼此重叠，并且发送器包括线圈

公开(公告)号：US09305253B2

公开(公告)日：2016-04-05

申请号：US13964446

申请日：2013-08-12

Applicant: Renesas Electronics Corporation

Inventor： Yasutaka Nakashiba ,  Hiroaki Ohkubo ,  Mitsuji Okada ,  Shigeharu Nakata ,  Shuuichi Kagawa

IPC: G06K19/06 ,  G06K19/073 ,  G11C7/24 ,  H03K19/0175

CPC classification number: G06K19/073 ,  G11C7/24 ,  H03K19/017509

Abstract: A memory card includes a memory that stores data, a driver that transmits the data received from the memory, and at least one transmitter that transmits the data received from the driver to a receiver provided in an external main unit. The driver and the at least one transmitter are provided in a single IC (integrated circuit) chip and are not overlapped with each other in a planar view.

Abstract translation: 存储卡包括存储数据的存储器，发送从存储器接收的数据的驱动器以及将从驱动器接收的数据发送到设置在外部主单元中的接收器的至少一个发送器。 驱动器和至少一个发射器设置在单个IC（集成电路）芯片中，并且在平面图中不彼此重叠。

公开(公告)号：US09117903B2

公开(公告)日：2015-08-25

申请号：US14204145

申请日：2014-03-11

Applicant: Renesas Electronics Corporation

Inventor： Akihiro Shimomura ,  Yutaka Akiyama ,  Saya Shimomura ,  Yasutaka Nakashiba

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/808 ,  H01L29/40 ,  H01L29/739

CPC classification number: H01L29/7827 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8083

Abstract: A buried layer of a second conductivity type and a lower layer of a second conductivity type are formed in a drift layer. A boundary insulating film is formed in the boundary between the lateral portion of the buried layer of a second conductivity type and the drift layer. The lower layer of a second conductivity type is in contact with the lower end of the buried layer of a second conductivity type and the lower end of the boundary insulating film. The buried layer of a second conductivity type is electrically connected to a source electrode. A high-concentration layer of a second conductivity type is formed in the surface layer of the buried layer of a second conductivity type.

Abstract translation: 在漂移层中形成第二导电类型的掩埋层和第二导电类型的下层。 边界绝缘膜形成在第二导电类型的掩埋层的横向部分与漂移层之间的边界中。 第二导电类型的下层与第二导电类型的掩埋层的下端和边界绝缘膜的下端接触。 第二导电类型的掩埋层与源电极电连接。 在第二导电类型的掩埋层的表面层中形成第二导电类型的高浓度层。

公开(公告)号：US09105501B2

公开(公告)日：2015-08-11

申请号：US14279603

申请日：2014-05-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka Nakashiba

IPC: H01L49/02 ,  G01R31/302 ,  G01R31/303 ,  H01L23/48 ,  H01L23/64 ,  G01R31/28 ,  H01L23/00

CPC classification number: H01L28/10 ,  G01R31/2886 ,  G01R31/3025 ,  G01R31/303 ,  H01L23/48 ,  H01L23/645 ,  H01L24/05 ,  H01L24/48 ,  H01L2224/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes a substrate, an internal circuit including a plurality of transistors provided over the substrate, an insulating film provided over the substrate, a bonding pad provided over the insulating film, an inductor being formed in the insulating film, the inductor carrying out a signal transmission/reception to/from an external device in a non-contact manner by an electromagnetic induction and being electrically coupled to the internal circuit. The inductor includes a first conducting layer, and the bonding pad includes a second conducting layer. The first conducting layer includes a lower level layer than the second conducting layer in a thickness direction of the substrate. In a plan view, the inductor includes a first portion overlapping the bonding pad and a second portion not overlapping the bonding pad.

Abstract translation: 半导体器件包括衬底，包括设置在衬底上的多个晶体管的内部电路，设置在衬底上的绝缘膜，设置在绝缘膜上的接合焊盘，形成在绝缘膜中的电感器，电感器执行 通过电磁感应以非接触方式向外部设备发送/接收信号，并且电耦合到内部电路。 电感器包括第一导电层，并且焊盘包括第二导电层。 第一导电层在衬底的厚度方向上包括比第二导电层低的层。 在平面图中，电感器包括与接合焊盘重叠的第一部分和不与接合焊盘重叠的第二部分。

公开(公告)号：US20140333149A1

公开(公告)日：2014-11-13

申请号：US14339414

申请日：2014-07-23

Applicant: Renesas Electronics Corporation

Inventor： Masaya Kawano ,  Yasutaka Nakashiba

IPC: H01F38/14

CPC classification number: H01F38/14 ,  H01F17/0013 ,  H01F27/2804 ,  H01F27/40 ,  H01F2017/0086 ,  H01F2027/2809 ,  H01F2038/143 ,  H01L23/535 ,  H01L27/1203 ,  H01L28/10 ,  H01L29/0649 ,  H01L2224/4813 ,  H01L2224/48137 ,  H01L2924/00014 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A circuit device includes a semiconductor substrate, a first inductor provided over the semiconductor substrate, and a second inductor provided over the semiconductor substrate and coupled to the first inductor. The first inductor and second inductor are wound in a same direction with each other from respective inner end portions to respective outer end portions thereof.

Abstract translation: 电路装置包括半导体衬底，设置在半导体衬底上的第一电感器和设置在半导体衬底上并耦合到第一电感器的第二电感器。 第一电感器和第二电感器从相应的内端部到相应的外端部彼此以相同方向缠绕。

公开(公告)号：US20140319691A1

公开(公告)日：2014-10-30

申请号：US14328458

申请日：2014-07-10

Applicant: Renesas Electronics Corporation

Inventor： Yasutaka Nakashiba

IPC: H01L23/522

CPC classification number: H01L23/5227 ,  H01L23/48 ,  H01L23/538 ,  H01L23/645 ,  H01L25/0655 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor chip having a multilayer interconnect, a first spiral inductor formed in the multilayer interconnect, and a second spiral inductor formed in the multilayer interconnect. The first spiral inductor and the second spiral inductor collectively include a line, the line being spirally wound in a first direction in the first spiral inductor toward outside of the first spiral inductor, and being spirally wound in a second direction in the second spiral inductor toward inside of the second spiral inductor. The first direction and the second direction are opposite directions.

Abstract translation: 半导体器件包括具有多层互连的半导体芯片，形成在多层互连中的第一螺旋感应电感器和形成在多层互连中的第二螺旋电感器。 第一螺旋电感器和第二螺旋电感器共同地包括一条线，该线路沿着第一方向在第一螺旋电感器中朝向第一螺旋电感器的外侧螺旋地卷绕，并且在第二螺旋电感器中沿第二方向螺旋地卷绕， 内部的第二个螺旋电感。 第一方向和第二方向是相反的方向。