公开(公告)号：US20240213357A1

公开(公告)日：2024-06-27

申请号：US18391388

申请日：2023-12-20

Applicant: Renesas Electronics Corporation

Inventor： Tomohiro IMAI ,  Yoshito NAKAZAWA

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7397 ,  H01L29/0696 ,  H01L29/41708 ,  H01L29/66348

Abstract: Performance of a semiconductor device is enhanced. A floating region covers a bottom surface of a trench in an active cell. In addition, the floating region covers a bottom surface of a trench in an inactive cell so as to reach a semiconductor substrate between a pair of trenches in the inactive cell. A distance between a base region and the floating region in the inactive cell is smaller than a distance between the base region and the floating region in the active cell.

公开(公告)号：US20180350910A1

公开(公告)日：2018-12-06

申请号：US15971139

申请日：2018-05-04

Applicant: Renesas Electronics Corporation

Inventor： Shigeaki SAITO ,  Yoshito NAKAZAWA ,  Hitoshi MATSUURA ,  Yukio TAKAHASHI

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/739

CPC classification number: H01L29/0696 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/7397

Abstract: The reliability of a semiconductor device is improved. A contact trench for coupling a field plate and a field limiting ring situated at the corner part of a semiconductor device is formed of a first straight line part and a second straight line part arranged line symmetrically with respect to the crystal orientation . Respective one ends of the first straight line part and the second straight line part are coupled at the crystal orientation , and the first straight line part and the second straight line part are set to extend in different directions from the crystal orientation and the crystal orientation .

公开(公告)号：US20160148923A1

公开(公告)日：2016-05-26

申请号：US15001767

申请日：2016-01-20

Applicant: Renesas Electronics Corporation

Inventor： Yoshito NAKAZAWA ,  Yuji YATSUDA

IPC: H01L27/02 ,  H01L29/78

CPC classification number: H01L29/7808 ,  H01L21/28008 ,  H01L21/28556 ,  H01L27/0255 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

Abstract: A semiconductor device having a field-effect transistor, including a trench in a semiconductor substrate, a first insulating film in the trench, an intrinsic polycrystalline silicon film over the first insulating film, and first conductivity type impurities in the intrinsic polycrystalline silicon film to form a first conductive film. The first conductive film is etched to form a first gate electrode in the trench. A second insulating film is also formed in the trench above the first insulating film and the first gate electrode, and a first conductivity type doped polycrystalline silicon film, having higher impurity concentration than the first gate electrode is formed over the second insulating film. The doped polycrystalline silicon film is provided in an upper part of the trench to form a second gate electrode.

Abstract translation: 一种具有场效应晶体管的半导体器件，包括半导体衬底中的沟槽，沟槽中的第一绝缘膜，第一绝缘膜上的本征多晶硅膜，以及本征多晶硅膜中的第一导电型杂质，以形成 第一导电膜。 蚀刻第一导电膜以在沟槽中形成第一栅电极。 在第二绝缘膜上形成有在第一绝缘膜和第一栅电极上方的沟槽中的第二绝缘膜，并且在第二绝缘膜上形成杂质浓度高于第一栅电极的第一导电型掺杂多晶硅膜。 掺杂多晶硅膜设置在沟槽的上部，以形成第二栅电极。

公开(公告)号：US20150011081A1

公开(公告)日：2015-01-08

申请号：US14492382

申请日：2014-09-22

Applicant: RENESAS ELECTRONICS CORPORATION ,  HITACHI ULSI SYSTEMS CO., LTD.

Inventor： Sumito NUMAZAWA ,  Yoshito NAKAZAWA ,  Masayoshi KOBAYASHI ,  Satoshi KUDO ,  Yasuo IMAI ,  Sakae KUBO ,  Takashi SHIGEMATSU ,  Akihiro OHNISHI ,  Kozo UESAWA ,  Kentaro OISHI

IPC: H01L21/28

CPC classification number: H01L21/28114 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

Abstract translation: 在制造具有沟槽栅极结构的MISFET的半导体器件的方法中，从半导体层的方向的深度方向上的第一导电类型的半导体层的主表面形成沟槽， 在沟槽的内表面上形成包括热氧化膜和沉积膜的栅极绝缘膜，并且在沟槽中形成栅电极之后，将杂质引入到第一导电类型的半导体衬底中以形成 用作沟道形成区域的第二导电类型的半导体区域，并且将杂质引入到第二导电类型的半导体区域中，以形成用作源极区域的第一导电类型的半导体区域。

公开(公告)号：US20140027842A1

公开(公告)日：2014-01-30

申请号：US14037103

申请日：2013-09-25

Applicant: Renesas Electronics Corporation

Inventor： Tomohiro TAMAKI ,  Yoshito NAKAZAWA

IPC: H01L29/78

CPC classification number: H01L29/0634 ,  H01L29/0615 ,  H01L29/063 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/66681 ,  H01L29/66727 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7823 ,  H01L29/7825

Abstract: A problem associated with n-channel power MOSFETs and the like that the following is caused even by relatively slight fluctuation in various process parameters is solved: source-drain breakdown voltage is reduced by breakdown at an end of a p-type body region in proximity to a portion in the vicinity of an annular intermediate region between an active cell region and a chip peripheral portion, arising from electric field concentration in that area. To solve this problem, the following measure is taken in a power semiconductor device having a superjunction structure in the respective drift regions of a first conductivity type of an active cell region, a chip peripheral region, and an intermediate region located therebetween: the width of at least one of column regions of a second conductivity type comprising the superjunction structure in the intermediate region is made larger than the width of the other regions.

Abstract translation: 解决了与各种工艺参数相对较轻的波动引起的n沟道功率MOSFET等相关的问题：源极 - 漏极击穿电压通过靠近p型体区域的端部的击穿而减小 到由该区域的电场浓度引起的活性单元区域与芯片周边部分之间的环状中间区域附近的部分。 为了解决这个问题，在第一导电类型的有源电池区域，芯片外围区域和位于它们之间的中间区域的各个漂移区域中，具有超结构结构的功率半导体器件采取以下措施： 使包括中间区域中的超结构结构的第二导电类型的列区域中的至少一个比其它区域的宽度大。

公开(公告)号：US20220102538A1

公开(公告)日：2022-03-31

申请号：US17405733

申请日：2021-08-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshito NAKAZAWA ,  Tomohiro IMAI

IPC: H01L29/739 ,  H01L29/66

Abstract: A semiconductor device according to one embodiment includes an IGBT having a p-type collector layer and an n-type field stop layer on a back surface of a silicon substrate. The n-type field stop layer is selectively provided on an upper side of the p-type collector layer such that a first end portion of the n-type field stop layer is separated from a first side surface of the silicon substrate by a predetermined distance, and an n-type drift layer is provided between the first side surface of the silicon substrate and the first end portion of the n-type field stop layer. An impurity concentration of the n-type drift layer is lower than an impurity concentration of the n-type field stop layer.

公开(公告)号：US20180090610A1

公开(公告)日：2018-03-29

申请号：US15829046

申请日：2017-12-01

Applicant: Renesas Electronics Corporation

Inventor： Yoshito NAKAZAWA ,  Yuji YATSUDA

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L29/40 ,  H01L29/06 ,  H01L27/02 ,  H01L21/285 ,  H01L29/45

CPC classification number: H01L29/7808 ,  H01L21/28008 ,  H01L21/28556 ,  H01L27/0255 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

Abstract: A semiconductor device including a field-effect transistor having source and drain source regions, first and second gate electrodes and a protective diode connected to the transistor. The first gate electrode is formed over a first gate insulating film in a lower part of a trench. The second gate electrode is formed over a second gate insulating film in an upper part of the trench. The first gate electrode includes a first polysilicon film, and the second gate electrode includes a second polysilicon film, wherein an impurity concentration of the first polysilicon film is lower than an impurity concentration of the second polysilicon film.

公开(公告)号：US20150200293A1

公开(公告)日：2015-07-16

申请号：US14590937

申请日：2015-01-06

Applicant: Renesas Electronics Corporation

Inventor： Satoshi EGUCHI ,  Yoshito NAKAZAWA

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/16

CPC classification number: H01L21/761 ,  H01L21/0415 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7811 ,  H01L29/861

Abstract: The reliability of a semiconductor device including a power semiconductor element is improved. The basic idea in embodiments is to make the band gap of a cell region smaller than the band gap of a peripheral region. Specifically, a lower band gap region having a smaller band gap than the band gap of an epitaxial layer is formed in the cell region. In addition, a higher band gap region having a larger band gap than the band gap of the epitaxial layer is formed in the peripheral region.

Abstract translation: 提高了包括功率半导体元件的半导体器件的可靠性。 实施例中的基本思想是使单元区域的带隙小于外围区域的带隙。 具体地，在单元区域中形成具有比外延层的带隙小的带隙的较低带隙区域。 此外，在周边区域中形成具有比外延层的带隙大的带隙的较高带隙区域。

公开(公告)号：US20140191309A1

公开(公告)日：2014-07-10

申请号：US14109208

申请日：2013-12-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Satoshi EGUCHI ,  Yoshito NAKAZAWA ,  Tomohiro TAMAKI

IPC: H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0619 ,  H01L29/0626 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/7802 ,  H01L29/7811

Abstract: When forming a super junction by the embedded epitaxial method, adjusting a taper angle of dry etching to form an inclined column is generally performed in trench forming etching, in order to prevent a reduction in breakdown voltage due to fluctuations in concentration in an embedded epitaxial layer. However, according to the examination by the present inventors, it has been made clear that such a method makes design more and more difficult in response to the higher breakdown voltage. In the present invention, the concentration in an intermediate substrate epitaxy column area in each substrate epitaxy column area configuring a super junction is made more than that in other areas within the substrate epitaxy column area, in a vertical power MOSFET having the super junction by the embedded epitaxial method.

Abstract translation: 当通过嵌入式外延法形成超级结时，通常在沟槽形成蚀刻中进行干蚀刻的锥角调整以形成倾斜的列，以便防止由嵌入的外延层中的浓度波动引起的击穿电压的降低 。 然而，根据本发明人的考察，已经清楚的是，这种方法使得设计越来越难以响应较高的击穿电压。 在本发明中，在构成超结的每个衬底外延柱区域中的中间衬底外延柱区域中的浓度比在衬底外延柱区域内的其它区域的浓度高， 嵌入式外延法。

公开(公告)号：US20220069111A1

公开(公告)日：2022-03-03

申请号：US17405648

申请日：2021-08-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tomohiro IMAI ,  Yoshito NAKAZAWA ,  Katsumi EIKYU

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/66

Abstract: An IGBT capable of handling high-speed switching while reducing a leakage current of a semiconductor device including the IGBT is provided. The semiconductor device according to one embodiment includes an IGBT including a p-type collector layer on a back surface of a silicon substrate and a dislocation suppressing layer for forming a hetero junction with silicon in the p-type collector layer. The dislocation suppressing layer includes a silicon germanium (SiGe) layer.