公开(公告)号：US20240079458A1

公开(公告)日：2024-03-07

申请号：US18322989

申请日：2023-05-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tomoki AYANO ,  Takahiro MARUYAMA ,  Yuya ABIKO

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/401 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7813

Abstract: A trench is formed in a semiconductor substrate. An insulating film is formed in the trench and on an upper surface of the semiconductor substrate. An ion implantation is performed to the insulating film. An etching treatment is performed to the insulating film, thereby a thickness of the insulating film is reduced. A conductive film is formed in the trench via the insulating film. In plan view, the trench extends in a Y-direction. The above-described ion implantation is performed from a direction inclined by a predetermined angle from an extending direction of a normal line with respect to the upper surface of the semiconductor substrate.

公开(公告)号：US20190207001A1

公开(公告)日：2019-07-04

申请号：US16299025

申请日：2019-03-11

Applicant: Renesas Electronics Corporation

Inventor： Yuya ABIKO ,  Natsuo YAMAGUCHI ,  Satoshi EGUCHI

IPC: H01L29/10 ,  H01L21/265 ,  H01L29/06 ,  H01L29/16 ,  H01L29/78 ,  H01L21/308 ,  H01L29/40 ,  H01L21/02 ,  H01L29/66 ,  H01L29/739

CPC classification number: H01L29/1095 ,  H01L21/02529 ,  H01L21/26586 ,  H01L21/308 ,  H01L29/0634 ,  H01L29/1608 ,  H01L29/404 ,  H01L29/66053 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7813

Abstract: In a vertical power MOSFET having a superjunction structure, the withstand voltage of the power MOSFET can be ensured even if the aspect ratios of an n-type column region and a p-type column region are increased so as to vary the impurity concentration of the p-type column region. P-type semiconductor regions PR1 are formed on the sides of an n-type column NC1 adjacent to a p-type column region PC1. In this configuration, the p-type semiconductor region PR1 is formed from the upper end of the n-type column region NC1 to about a half depth of a height from the upper end to the lower end of the side of the n-type column region NC1. This inclines the sides of the overall p-type column region including the p-type semiconductor regions PR1 and the p-type column region PC1.

公开(公告)号：US20180076313A1

公开(公告)日：2018-03-15

申请号：US15640375

申请日：2017-06-30

Applicant: Renesas Electronics Corporation

Inventor： Yuya ABIKO ,  Satoshi EGUCHI ,  Shigeaki SAITO ,  Daisuke TANIGUCHI ,  Natsuo YAMAGUCHI

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7802 ,  H01L21/2205 ,  H01L21/2251 ,  H01L21/2253 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/66712 ,  H01L29/7811 ,  H01L29/8611

Abstract: Properties of a semiconductor device are improved. A semiconductor device having a superjunction structure, in which p-type column regions and n-type column regions are periodically arranged, is configured as follows. Each n-type column region has a vertical section including an n-type epitaxial layer located between trenches and a tapered embedded n-type epitaxial film disposed on a side face of the trench. Each p-type column region includes an embedded p-type epitaxial film disposed within the trench. The tapered embedded n-type epitaxial film is thus provided on the sidewall of the trench in which the p-type column region is to be disposed, thereby the p-type column region is allowed to have an inverted trapezoidal shape, leading to an increase in margin for a variation in concentration of a p-type impurity in the p-type column region. On resistance can be reduced by lateral diffusion of an n-type impurity (for example, As).

公开(公告)号：US20130189819A1

公开(公告)日：2013-07-25

申请号：US13742489

申请日：2013-01-16

Applicant: Renesas Electronics Corporation

Inventor： Satoshi EGUCHI ,  Yuya ABIKO ,  Junichi KOGURE

IPC: H01L29/66

CPC classification number: H01L29/7802 ,  H01L21/02639 ,  H01L21/26506 ,  H01L21/26566 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7842 ,  H01L29/7848

Abstract: In the manufacturing steps of a super-junction power MOSFET having a drift region having a super junction structure, after the super junction structure is formed, introduction of a body region and the like and heat treatment related thereto are typically performed. However, in the process thereof, a dopant in each of P-type column regions and the like included in the super junction structure is diffused to result in a scattered dopant profile. This causes problems such as degradation of a breakdown voltage when a reverse bias voltage is applied between a drain and a source and an increase in ON resistance. According to the present invention, in a method of manufacturing a silicon-based vertical planar power MOSFET, a body region forming a channel region is formed by selective epitaxial growth.

Abstract translation: 在具有超结结构的漂移区域的超结功率MOSFET的制造步骤中，在形成超结结构之后，通常进行体区等的引入和与其相关的热处理。 然而，在其过程中，包含在超结结构中的每个P型列区域等中的掺杂剂被扩散以产生散射掺杂剂分布。 这导致了当在漏极和源极之间施加反向偏置电压和导通电阻增加时诸如击穿电压劣化的问题。 根据本发明，在制造硅基垂直平面功率MOSFET的方法中，通过选择性外延生长形成形成沟道区的体区。

公开(公告)号：US20230299194A1

公开(公告)日：2023-09-21

申请号：US18061673

申请日：2022-12-05

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuto OMIZU ,  Yuya ABIKO

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L21/225 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/063 ,  H01L29/407 ,  H01L21/2253 ,  H01L21/26513 ,  H01L29/66734

Abstract: Disclosed is a technique for improving performance of a semiconductor device having a trench gate type power MOSFET. Concretely, a method of manufacturing a semiconductor device having a trench gate type power MOSFET comprising: forming a trench in a semiconductor substrate; introducing both of a p-type impurity(Boron) and carbon (C) into a bottom surface of the trench to form a p-type impurity introduced region; forming a gate electrode to fill the trench; forming a channel forming region and a source region at the side of the trench in which the gate electrode is filled; and subjecting a heat treatment to the p-type impurity introduced region to form an electric field relaxation layer having suppressed crystal defects and a controlled shape.

公开(公告)号：US20180012959A1

公开(公告)日：2018-01-11

申请号：US15700669

申请日：2017-09-11

Applicant: Renesas Electronics Corporation

Inventor： Akio ICHIMURA ,  Satoshi EGUCHI ,  Tetsuya IIDA ,  Yuya ABIKO

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/10 ,  H01L29/417

CPC classification number: H01L29/0634 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/41766 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/7811

Abstract: A super junction structure having a high aspect ratio is formed. An epitaxial layer is dividedly formed in layers using the trench fill process, and when each of the layers has been formed, trenches are formed in that layer. For example, when a first epitaxial layer has been formed, first trenches are formed in the epitaxial layer. Subsequently, when a second epitaxial layer has been formed, second trenches are formed in the epitaxial layer. Subsequently, when a third epitaxial layer has been formed, third trenches are formed in the third epitaxial layer.

公开(公告)号：US20170154984A1

公开(公告)日：2017-06-01

申请号：US15355469

申请日：2016-11-18

Applicant: Renesas Electronics Corporation

Inventor： Satoshi EGUCHI ,  Hitoshi MATSUURA ,  Yuya ABIKO

IPC: H01L29/739 ,  H01L21/324 ,  H01L29/66 ,  H01L21/265 ,  H01L29/06 ,  H01L29/32

CPC classification number: H01L29/7396 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/324 ,  H01L29/0634 ,  H01L29/0688 ,  H01L29/1095 ,  H01L29/32 ,  H01L29/404 ,  H01L29/66333 ,  H01L29/6634

Abstract: Reduction of power consumption of a semiconductor device is aimed. The semiconductor device includes a cell region where a vertical power MOSFET is formed and an intermediate region surrounding the cell region. In each of the cell region and the intermediate region, a plurality of p-type column regions and a plurality of n-type column regions are alternately formed. The n-type column region arranged in the cell region has a defect region formed therein, whereas the n-type column region arranged in the intermediate region does not have the defect region. A defect density in the n-type column region arranged in the cell region is larger than that in the n-type column region arranged in the intermediate region.

公开(公告)号：US20160204192A1

公开(公告)日：2016-07-14

申请号：US14965899

申请日：2015-12-11

Applicant: Renesas Electronics Corporation

Inventor： Yuya ABIKO ,  Satoshi EGUCHI ,  Akio ICHIMURA ,  Natsuo YAMAGUCHI ,  Tetsuya IIDA

IPC: H01L29/06 ,  H01L27/06 ,  H01L21/8234 ,  H01L29/417

CPC classification number: H01L29/0696 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823487 ,  H01L27/0688 ,  H01L29/06 ,  H01L29/0634 ,  H01L29/0684 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/66727 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7811

Abstract: In a semiconductor device including a super junction structure that p-type columns and n-type columns are periodically arranged, a depth of a p-type column region in a cell region that a semiconductor element is formed is made shallower than a depth of a p-type column region in an intermediate region which surrounds the cell region. Thereby, a breakdown voltage of the cell region becomes lower than a breakdown voltage of the intermediate region. An avalanche breakdown phenomenon is caused to occur preferentially in the cell region in which even when an avalanche current is generated, the current is dispersed and smoothly flows. Thereby, it is possible to avoid local current constriction and breakage incidental thereto and consequently it becomes possible to improve avalanche resistance (an avalanche current amount with which a semiconductor device comes to be broken).

Abstract translation: 在包括p型列和n型列周期性排列的超结结构的半导体器件中，形成半导体元件的单元区域中的p型列区的深度比深度 在围绕细胞区域的中间区域中的p型列区域。 由此，电池区域的击穿电压变得低于中间区域的击穿电压。 即使在产生雪崩电流的电池区域中，优先发生雪崩击穿现象，电流分散而平稳地流动。 由此，能够避免局部的电流收缩和附带的断线，能够提高雪崩电阻（半导体装置的崩溃电流量的破坏）。

公开(公告)号：US20160049466A1

公开(公告)日：2016-02-18

申请号：US14826075

申请日：2015-08-13

Applicant: Renesas Electronics Corporation

Inventor： Yuya ABIKO ,  Akio ICHIMURA ,  Toshiaki IGARASHI ,  Yasuhiro SHIRAI

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/04 ,  H01L29/78

CPC classification number: H01L29/0634 ,  H01L29/045 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/7811 ,  H01L29/7827

Abstract: To improve characteristics of a semiconductor device (vertical power MOSFET). A spiral p-type column region having a corner is formed in a peripheral region surrounding a cell region in which a semiconductor element is formed. In an epitaxial layer of the peripheral region surrounding the cell region in which the semiconductor element is formed, a trench spirally surrounding the cell region and having the first and second side faces making up the corner is formed and the trench is filled with the epitaxial layer. By spirally arranging the p-type column region (n-type column region) in such a manner, a drop in a withstand voltage margin due to a hot spot can be avoided. In addition, the continuity of the p-type column region (n-type column region) is maintained. As a result, electric field concentration is alleviated step by step toward the outer periphery and the withstand voltage is therefore increased.

Abstract translation: 改善半导体器件（垂直功率MOSFET）的特性。 在围绕形成有半导体元件的单元区域的周边区域中形成具有角部的螺旋状p型列区域。 在围绕形成有半导体元件的单元区域的外围区域的外延层中，形成螺旋状包围单元区域并且具有构成拐角的第一和第二侧面的沟槽，并且沟槽被外延层填充 。 通过以这种方式螺旋地排列p型列区域（n型列区域），可以避免由于热点导致的耐受电压裕度的下降。 此外，保持p型列区域（n型列区域）的连续性。 结果，逐渐朝向外周逐渐减小电场浓度，耐压提高。

公开(公告)号：US20150333118A1

公开(公告)日：2015-11-19

申请号：US14705057

申请日：2015-05-06

Applicant: Renesas Electronics Corporation

Inventor： Satoshi EGUCHI ,  Tetsuya IIDA ,  Akio ICHIMURA ,  Yuya ABIKO

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/7811 ,  H01L21/265 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/42372 ,  H01L29/66477 ,  H01L29/66712

Abstract: To provide a semiconductor device including a power semiconductor element having improved reliability. The semiconductor device has a cell region and a peripheral region formed outside the cell region. The n type impurity concentration of n type column regions in the cell region is made higher than that of n type column regions comprised of an epitaxial layer in the peripheral region. Further, a charge balance is kept in each of the cell region and the peripheral region and each total electric charge is set so that a total electric charge of first p type column regions and a total electric charge of n type column regions in the cell region become larger than a total electric charge of third p type column regions and n type column regions comprised of an epitaxial layer in the peripheral region, respectively.

Abstract translation: 提供包括具有提高的可靠性的功率半导体元件的半导体器件。 半导体器件具有形成在单元区域外的单元区域和周边区域。 使单元区域中的n型列区域的n型杂质浓度高于在外围区域中由外延层构成的n型列区域的n型杂质浓度。 此外，在单元区域和外围区域中的每一个中保持电荷平衡，并且设置每个总电荷，使得第一p型列区域的总电荷和单元区域中的n型列区域的总电荷 分别变得大于第三p型列区域的总电荷和由周边区域中的外延层构成的n型列区域。