公开(公告)号：US20120147660A1

公开(公告)日：2012-06-14

申请号：US13401665

申请日：2012-02-21

Applicant: CHRISTOPHE CHEVALLIER ,  ROBERT NORMAN

Inventor： CHRISTOPHE CHEVALLIER ,  ROBERT NORMAN

IPC: G11C11/00

CPC classification number: G11C13/0035 ,  G11C5/005 ,  G11C5/02 ,  G11C11/16 ,  G11C13/0002 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/77

Abstract: Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer.

Abstract translation: 公开了用于恢复存储器中的数据的电路和方法。 存储器可以包括非易失性两端交叉点阵列的至少一层，其包括将数据存储为多个电导率分布并且在没有电力的情况下保存存储的数据的多个两端存储器元件。 在一段时间内，指示存储的数据的逻辑值可能漂移，使得如果逻辑值不被恢复，则所存储的数据可能被破坏。 每个存储器的至少一部分可以具有与存储器电耦合的电路重写或恢复的数据。 可以使用其他电路来确定用于对存储器执行恢复操作的调度，并且恢复操作可以由内部或外部信号或事件来触发。 电路可以定位在逻辑层中，并且存储器可以在逻辑层上制造。

公开(公告)号：US20120069620A1

公开(公告)日：2012-03-22

申请号：US13303012

申请日：2011-11-22

Applicant: ROBERT NORMAN

Inventor： ROBERT NORMAN

IPC: G11C5/02

CPC classification number: G11C5/04 ,  G06F12/0638 ,  G06F2212/7208 ,  G11C5/02 ,  G11C11/005 ,  Y02D10/13

Abstract: A multiple-type memory is disclosed. The multiple-type memory includes memory blocks in communication with control logic blocks. The memory blocks and the control logic blocks are configured to emulate a plurality of memory types. The memory blocks can be configured into a plurality of memory planes that are vertically stacked upon one another. The vertically stacked memory planes may be used to increase data storage density and/or the number of memory types that can be emulated by the multiple-type memory. Each memory plane can emulate one or more memory types. The control logic blocks can be formed in a substrate (e.g., a silicon substrate including CMOS circuitry) and the memory blocks or the plurality of memory planes can be positioned over the substrate and in communication with the control logic blocks. The multiple-type memory may be non-volatile so that stored data is retained in the absence of power.

Abstract translation: 公开了一种多式存储器。 多类型存储器包括与控制逻辑块通信的存储器块。 存储器块和控制逻辑块被配置为模拟多个存储器类型。 存储器块可以被配置成彼此垂直堆叠的多个存储器平面。 可以使用垂直堆叠的存储器平面来增加数据存储密度和/或可由多型存储器仿真的存储器类型的数量。 每个存储器平面可以模拟一个或多个存储器类型。 控制逻辑块可以形成在衬底（例如，包括CMOS电路的硅衬底）中，并且存储器块或多个存储器平面可以位于衬底上并与控制逻辑块通信。 多类型存储器可以是非易失性的，使得存储的数据在没有电力的情况下被保留。

公开(公告)号：US20120063239A1

公开(公告)日：2012-03-15

申请号：US13303002

申请日：2011-11-22

Applicant: ROBERT NORMAN

Inventor： ROBERT NORMAN

IPC: G11C7/00

CPC classification number: G06F12/06 ,  G06F13/1694 ,  G11C11/005 ,  Y02D10/13 ,  Y02D10/14

Abstract: Circuitry and a method for indicating a multiple-type memory is disclosed. The multiple-type memory includes memory blocks in communication with control logic blocks. The memory blocks and the control logic blocks are configured to emulate a plurality of memory types. The memory blocks can be configured into a plurality of vertically stacked memory planes. The vertically stacked memory planes may be used to increase data storage density and/or the number of memory types that can be emulated by the multiple-type memory. Each memory plane can emulate one or more memory types. The control logic blocks can be formed in a substrate (e.g., a silicon substrate including CMOS circuitry) and the memory blocks or the plurality of memory planes can be positioned over the substrate and in communication with the control logic blocks. The multiple-type memory may be non-volatile so that stored data is retained in the absence of power.

Abstract translation: 公开了一种用于指示多型存储器的电路和方法。 多类型存储器包括与控制逻辑块通信的存储器块。 存储器块和控制逻辑块被配置为模拟多个存储器类型。 存储器块可以被配置成多个垂直堆叠的存储器平面。 可以使用垂直堆叠的存储器平面来增加数据存储密度和/或可由多型存储器仿真的存储器类型的数量。 每个存储器平面可以模拟一个或多个存储器类型。 控制逻辑块可以形成在衬底（例如，包括CMOS电路的硅衬底）中，并且存储器块或多个存储器平面可以位于衬底上并与控制逻辑块通信。 多类型存储器可以是非易失性的，使得存储的数据在没有电力的情况下被保留。

公开(公告)号：US20120063200A1

公开(公告)日：2012-03-15

申请号：US13302990

申请日：2011-11-22

Applicant: ROBERT NORMAN

Inventor： ROBERT NORMAN

IPC: G11C11/21

CPC classification number: G11C8/16 ,  G06F5/10 ,  G11C7/10 ,  G11C7/22 ,  G11C13/00 ,  G11C13/0007 ,  G11C19/287 ,  G11C2213/31 ,  G11C2213/71

Abstract: A FIFO with data storage implemented with non-volatile third dimension memory cells is disclosed. The non-volatile third dimension memory cells can be fabricated BEOL on top of a substrate that includes FEOL fabricated active circuitry configured for data operations on the BEOL memory cells. Other components of the FIFO that require non-volatile data storage can also be implemented as registers or the like using the BEOL non-volatile third dimension memory cells so that power to the FIFO can be cycled and data is retained. The BEOL non-volatile third dimension memory cells can be configured in a single layer of memory or in multiple layers of memory. An IC that includes the FIFO can also include one or more other memory types that are emulated using the BEOL non-volatile third dimension memory cells and associated FEOL circuitry configured for data operations on those memory cells.

Abstract translation: 公开了一种使用非易失性第三维存储器单元实现数据存储的FIFO。 非易失性第三维存储器单元可以在衬底之上制造BEOL，其包括配置用于在BEOL存储器单元上的数据操作的FEOL制造的有源电路。 需要非易失性数据存储的FIFO的其他组件也可以使用BEOL非易失性第三维存储器单元来实现为寄存器等，使得FIFO的功率可以循环并且数据被保留。 BEOL非易失性第三维存储单元可以配置在单层存储器或多层存储器中。 包括FIFO的IC还可以包括使用BEOL非易失性第三维存储器单元和配置用于在那些存储器单元上的数据操作的相关FEOL电路来仿真的一个或多个其他存储器类型。

公开(公告)号：US20120217466A1

公开(公告)日：2012-08-30

申请号：US13455002

申请日：2012-04-24

Applicant: ROBERT NORMAN

Inventor： ROBERT NORMAN

IPC: H01L27/24

CPC classification number: H03G1/0088 ,  H03G3/001 ,  H03H11/24

Abstract: A digital potentiometer using third dimensional memory includes a switch configured to electrically couple one or more resistive elements with a first pin and a second pin, and a non-volatile register configured to control the switch. In one example, the non-volatile register can include a BEOL non-volatile memory element, such as a third dimensional memory element. The non-volatile register can include a FEOL active circuitry portion that is electrically coupled with the BEOL non-volatile memory element to implement the non-volatile register. The resistive elements can be BEOL resistive elements that can be fabricated on the same plane or a different plane than the BEOL non-volatile memory elements. The BEOL non-volatile memory elements and the BEOL resistive elements can retain stored data in the absence of power and the stored data can be non-destructively determined by application of a read voltage.

Abstract translation: 使用第三维存储器的数字电位器包括被配置为将一个或多个电阻元件与第一引脚和第二引脚电耦合的开关以及被配置为控制开关的非易失性寄存器。 在一个示例中，非易失性寄存器可以包括诸如第三维存储器元件的BEOL非易失性存储器元件。 非易失性寄存器可以包括与BEOL非易失性存储器元件电耦合以实现非易失性寄存器的FEOL有源电路部分。 电阻元件可以是可以制造在与BEOL非易失性存储器元件相同的平面或不同平面上的BEOL电阻元件。 BEOL非易失性存储器元件和BEOL电阻元件可以在没有电力的情况下保留存储的数据，并且存储的数据可以通过应用读取电压而非破坏性地确定。

公开(公告)号：US20120208595A1

公开(公告)日：2012-08-16

申请号：US13455028

申请日：2012-04-24

Applicant: ROBERT NORMAN

Inventor： ROBERT NORMAN

IPC: H04W88/02

CPC classification number: G06F12/0238 ,  G06F9/455 ,  G06F12/0638 ,  G06F2212/2024 ,  Y02D10/13

Abstract: A cellular telephone using a memory array that is directly addressed and non-volatile is disclosed. The memory array can be used to replace and emulate multiple memory types such as DRAM, SRAM, non-volatile RAM, FLASH memory, and a non-volatile memory card, for example. The memory array may be randomly accessed. Data stored in the memory array is retained in the absence of electrical power. One or more memory arrays may be used in the cellular telephone. At least one of the memory arrays may be in the form of a removable memory card.

Abstract translation: 公开了一种使用直接寻址和非易失性存储器阵列的蜂窝电话。 存储器阵列可以用于替换和仿真多种存储器类型，例如DRAM，SRAM，非易失性RAM，FLASH存储器和非易失性存储卡。 可以随机访问存储器阵列。 存储在存储器阵列中的数据在没有电力的情况下被保留。 在蜂窝电话中可以使用一个或多个存储器阵列。 存储器阵列中的至少一个可以是可移动存储卡的形式。

公开(公告)号：US20120206980A1

公开(公告)日：2012-08-16

申请号：US13455018

申请日：2012-04-24

Applicant: ROBERT NORMAN

Inventor： ROBERT NORMAN

IPC: G11C7/10

CPC classification number: G11C7/1096 ,  G11C5/02 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/1087 ,  G11C8/10 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3427 ,  G11C2013/0085 ,  G11C2013/0088 ,  G11C2213/71 ,  G11C2216/14

Abstract: Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles.

Abstract translation: 本发明的实施例一般涉及数据存储和计算机存储器，更具体地，涉及用于访问实现例如第三维存储器技术的多层存储器中的存储器的系统，集成电路和方法。 在具体实施例中，集成电路被配置为实现写入缓冲器以访问多层存储器。 例如，集成电路可以包括设置在多层存储器中的存储单元。 在一个实施例中，存储器单元可以是第三维存储器单元。 集成电路还可以包括可以与写入缓冲器不同的读取缓冲器。 在至少一个实施例中，写入缓冲器的大小可以作为写周期的函数。 每层存储器可以包括多个两端存储元件，其在不存在功率的情况下保存存储的数据，并将数据存储为多个导电率分布。

公开(公告)号：US20120057394A1

公开(公告)日：2012-03-08

申请号：US13296979

申请日：2011-11-15

Applicant: ROBERT NORMAN

Inventor： ROBERT NORMAN

IPC: G11C11/00

CPC classification number: G11C7/24 ,  G11C5/02

Abstract: The various embodiments of the invention relate generally to semiconductors and memory technology. More specifically, the various embodiment and examples of the invention relate to memory devices, systems, and methods that protect data stored in one or more memory devices from unauthorized access. The memory device may include third dimension memory that is positioned on top of a logic layer that includes active circuitry in communication with the third dimension memory. The third dimension memory may include multiple layers of memory that are vertically stacked upon each other. Each layer of memory may include a plurality of two-terminal memory elements and the two-terminal memory elements can be arranged in a two-terminal cross-point array configuration. At least a portion of one or more of the multiple layers of memory may include an obfuscation layer configured to conceal data stored in one or more of the multiple layers of memory.

Abstract translation: 本发明的各种实施例一般涉及半导体和存储器技术。 更具体地，本发明的各种实施例和示例涉及保护存储在一个或多个存储器装置中的数据免于未授权访问的存储器件，系统和方法。 存储器件可以包括位于包括与第三维存储器通信的有源电路的逻辑层顶部上的第三维存储器。 第三维存储器可以包括彼此垂直堆叠的多层存储器。 每个存储器层可以包括多个两端存储器元件，并且两端存储器元件可以被布置成两端交叉点阵列配置。 存储器的多层中的一个或多个的至少一部分可以包括被配置为隐藏存储在多层存储器中的一个或多个层中的数据的混淆层。

公开(公告)号：US20110310658A1

公开(公告)日：2011-12-22

申请号：US13224173

申请日：2011-09-01

Applicant: ROBERT NORMAN

Inventor： ROBERT NORMAN

IPC: G11C11/00 ,  G11C7/00

CPC classification number: H01L45/08 ,  G06F17/5045 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0009 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/005 ,  G11C2013/009 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/53 ,  G11C2213/54 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1625

Abstract: Combined memories in integrated circuits are described, including determining a first requirement for logic blocks, determining a second requirement for memory blocks including a vertical configuration for the memory blocks, and compiling a design for the integrated circuit using the first requirement and the second requirement. The memory blocks may include non-volatile two-terminal cross-point memory arrays. The non-volatile two-terminal cross-point memory arrays can be formed on top of a logic plane. The logic plane can be fabricated in a substrate. The non-volatile two-terminal cross-point memory arrays may be vertically stacked upon one another to form a plurality of memory planes. The memory planes can be portioned into sub-planes. One or more different memory types such as Flash, SRAM, DRAM, and ROM can be emulated by the plurality of memory planes and/or sub-planes. The non-volatile two-terminal cross-point memory arrays can include a plurality of two-terminal memory elements.

Abstract translation: 描述了集成电路中的组合存储器，包括确定对逻辑块的第一要求，确定包括用于存储器块的垂直配置的存储器块的第二要求，以及使用第一要求和第二要求编译集成电路的设计。 存储器块可以包括非易失性两端交叉点存储器阵列。 非易失性双端子交叉点存储器阵列可以形成在逻辑平面的顶部。 逻辑平面可以在衬底中制造。 非易失性双端子交叉点存储器阵列可以彼此垂直地堆叠以形成多个存储器平面。 存储器平面可以分成子平面。 可以通过多个存储器平面和/或子平面来仿真一个或多个不同的存储器类型，例如闪存，SRAM，DRAM和ROM。 非易失性两端交叉点存储器阵列可以包括多个两端存储元件。

公开(公告)号：US20110304355A1

公开(公告)日：2011-12-15

申请号：US13216052

申请日：2011-08-23

Applicant: ROBERT NORMAN

Inventor： ROBERT NORMAN

IPC: H03K19/177

CPC classification number: H03K19/1776 ,  H03K19/17748 ,  H03K19/1778 ,  H03K19/17796

Abstract: A Programmable Logic Device (PLD) structure using third dimensional memory is disclosed. The PLD structure includes a switch configured to couple a polarity of a signal (e.g., an input signal applied to an input) to a routing line and a non-volatile register configured to control the switch. The non-volatile register may include a non-volatile memory element, such as a third dimension memory element. The non-volatile memory element may be a two-terminal memory element that retains stored data in the absence of power and stores data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the two terminals. New data can be written to the two-terminal memory element by applying a write voltage across the two terminals. Logic and other active circuitry can be positioned in a substrate and the non-volatile memory element can be positioned on top of the substrate.

Abstract translation: 公开了一种使用第三维存储器的可编程逻辑器件（PLD）结构。 PLD结构包括被配置为将信号的极性（例如，施加到输入的输入信号）耦合到路由线路的开关和被配置为控制开关的非易失性寄存器。 非易失性寄存器可以包括诸如第三维存储元件的非易失性存储元件。 非易失性存储器元件可以是在没有电力的情况下保存存储的数据并将数据存储为可以通过在两个端子上施加读取电压而被非破坏性地感测的多个电导率分布的两端存储元件。 可以通过在两个端子上施加写入电压将新数据写入到两端存储元件。 逻辑和其它有源电路可以被定位在衬底中，并且非易失性存储元件可以被定位在衬底的顶部上。