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    Vertical metal-insulator-metal (MIM) capacitor using gate stack, gate spacer and contact via
    13.
    发明授权
    Vertical metal-insulator-metal (MIM) capacitor using gate stack, gate spacer and contact via 有权
    垂直金属绝缘体金属（MIM）电容器，采用栅极叠层，栅极隔离和接触通孔

    公开(公告)号：US08017997B2

    公开(公告)日：2011-09-13

    申请号：US12344697

    申请日：2008-12-29

    申请人： Ramachandra Divakaruni ,  Mukta G. Farooq ,  Jeffrey P. Gambino ,  Kevin S. Petrarca

    发明人： Ramachandra Divakaruni ,  Mukta G. Farooq ,  Jeffrey P. Gambino ,  Kevin S. Petrarca

    IPC分类号： H01L29/76 ,  H01L29/94

    CPC分类号： H01L28/60 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/0629 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor structure including a vertical metal-insulator-metal capacitor, and a method for fabricating the semiconductor structure including the vertical metal-insulator-metal capacitor, each use structural components from a dummy metal oxide semiconductor field effect transistor located and formed over an isolation region located over a semiconductor substrate. The dummy metal oxide field effect transistor may be formed simultaneously with a metal oxide semiconductor field effect transistor located over a semiconductor substrate that includes the isolation region. The metal-insulator-metal capacitor uses a gate as a capacitor plate, a uniform thickness gate spacer as a gate dielectric and a contact via as another capacitor plate. The uniform thickness gate spacer may include a conductor layer for enhanced capacitance. A mirrored metal-insulator-metal capacitor structure that uses a single contact via may also be used for enhanced capacitance.

    摘要翻译： 包括垂直金属 - 绝缘体 - 金属电容器的半导体结构以及包括垂直金属 - 绝缘体 - 金属电容器的半导体结构的制造方法，每个都使用位于隔离层上并形成的虚设金属氧化物半导体场效应晶体管的结构部件 区域位于半导体衬底上。 虚拟金属氧化物场效应晶体管可以与位于包括隔离区域的半导体衬底之上的金属氧化物半导体场效应晶体管同时形成。 金属 - 绝缘体 - 金属电容器使用栅极作为电容器板，均匀厚度的栅极间隔物作为栅极电介质和作为另一个电容器板的接触通孔。 均匀厚度的栅极间隔物可以包括用于增强电容的导体层。 使用单个接触通孔的镜像金属 - 绝缘体 - 金属电容器结构也可用于增强电容。

    SELF-ALIGNED PATTERNED ETCH STOP LAYERS FOR SEMICONDUCTOR DEVICES
    14.
    发明申请
    SELF-ALIGNED PATTERNED ETCH STOP LAYERS FOR SEMICONDUCTOR DEVICES 失效
    用于半导体器件的自对准图形蚀刻停止层

    公开(公告)号：US20110092069A1

    公开(公告)日：2011-04-21

    申请号：US12582137

    申请日：2009-10-20

    申请人： Kangguo Cheng ,  Lawrence A. Clevenger ,  Johnathan E. Faltermeier ,  Stephan Grunow ,  Kaushik A. Kumar ,  Kevin S. Petrarca

    发明人： Kangguo Cheng ,  Lawrence A. Clevenger ,  Johnathan E. Faltermeier ,  Stephan Grunow ,  Kaushik A. Kumar ,  Kevin S. Petrarca

    IPC分类号： H01L21/3205 ,  H01L21/768

    CPC分类号： H01L21/76808 ,  H01L21/76802 ,  H01L21/7681 ,  H01L21/76825 ,  H01L21/76829

    摘要： A method of forming a semiconductor device includes patterning a photoresist layer formed over a homogeneous semiconductor device layer to be etched; subjecting the semiconductor device to an implant process that selectively implants a sacrificial etch stop layer that is self-aligned in accordance with locations of features to be etched within the homogeneous semiconductor device layer, and at a desired depth for the features to be etched; etching a feature pattern defined by the patterned photoresist layer into the homogenous semiconductor device layer, stopping on the implanted sacrificial etch stop layer; and removing remaining portion of the implanted sacrificial etch stop layer prior to filling the etched feature pattern with a fill material.

    摘要翻译： 形成半导体器件的方法包括：图案化在待蚀刻的均匀半导体器件层上形成的光致抗蚀剂层; 对半导体器件进行注入工艺，该注入工艺根据待均匀半导体器件层内待蚀刻的特征的位置以及在要蚀刻的特征的期望深度选择性地埋入自对准的牺牲蚀刻停止层; 将由图案化的光致抗蚀剂层限定的特征图案蚀刻成均匀的半导体器件层，停止在注入的牺牲蚀刻停止层上; 以及在用填充材料填充蚀刻的特征图案之前去除注入的牺牲蚀刻停止层的剩余部分。