公开(公告)号：US20110147068A1

公开(公告)日：2011-06-23

申请号：US12641381

申请日：2009-12-18

Applicant: Joseph J. Cahill ,  Anand Haridass ,  Roger D. Weekly

Inventor： Joseph J. Cahill ,  Anand Haridass ,  Roger D. Weekly

IPC: H05K1/11 ,  G06F17/50

CPC classification number: H05K1/0251 ,  G06F17/5077 ,  H05K1/162 ,  H05K2201/09509 ,  H05K2201/09536

Abstract: An apparatus is provided that comprises a plurality of signaling planes providing signal pathways and at least one internal reference plane providing either a voltage or a ground connection. The at least one internal reference plane are provided between at least two of the signaling planes. The apparatus further comprises a signal blind/buried via coupling a signal pathway of a first one of the at least two signaling planes with a signal pathway of a second one of the at least two signaling planes. The blind/buried via runs through the at least one internal reference plane. The apparatus also comprises at least one first conductive feature in the first one of the at least two signaling planes. The at least one first conductive feature is in close proximity to the signal blind/buried via and increases the capacitive coupling of currents in the reference planes of the apparatus.

Abstract translation: 提供了一种装置，其包括提供信号路径的多个信令平面和提供电压或接地连接的至少一个内部参考平面。 所述至少一个内部参考平面设置在至少两个信令平面之间。 该装置还包括通过将至少两个信令平面中的第一个信号平面的第一信号平面的信号路径与至少两个信令平面中的第二信号平面的信号路径耦合而进行信号盲/掩蔽。 盲/埋通孔穿过至少一个内部参考平面。 该装置还包括至少两个信令平面中的第一个中的至少一个第一导电特征。 至少一个第一导电特征与信号盲/掩埋通孔紧密接近，并且增加了装置参考平面中电流的电容耦合。

公开(公告)号：US20110085313A1

公开(公告)日：2011-04-14

申请号：US12579051

申请日：2009-10-14

Applicant: John L. Colbert ,  Arvind K. Sinha ,  Roger D. Weekly

Inventor： John L. Colbert ,  Arvind K. Sinha ,  Roger D. Weekly

IPC: H05K1/11 ,  G06F17/50

CPC classification number: H05K1/144 ,  G11C5/025 ,  H05K1/113 ,  H05K1/114 ,  H05K1/141 ,  H05K3/0058 ,  H05K3/325 ,  H05K2201/044 ,  H05K2201/10378 ,  H05K2201/10545 ,  H05K2201/10719 ,  H05K2201/2009

Abstract: A system, method, and motherboard assembly are described for interconnecting and distributing signals and power between co-planar boards that function as a single motherboard. The motherboard assembly includes a multilayered first printed circuit board having opposed parallel first and second surfaces, each having at least one land grid array (LGA) disposed thereon. The assembly further includes at least one wiring layer (Y) designed to only electrically interconnect components on or within the first PCB, and at least one wiring layer (X) designed to only electrically connect the components on the first PCB to a multilayered second PCB. The multilayered second PCB has opposed parallel first and second surfaces, the first surface having at least one LGA disposed thereon. It further includes at least one wiring layer (V) designed to only electrically interconnect components on or within the second PCB, and at least one layer (X) designed to only electrically interconnect the components on the second PCB with the components on the first PCB. A first LGA interposer couples to the LGA disposed on the first surface of the first PCB, and electrically connects at least one component to the first PCB. A second LGA interposer is sandwiched between and couples to the LGA disposed on the second surface of the first PCB and to the LGA disposed on the first surface of the second PCB. It electrically connects the first PCB to components on the second PCB.

Abstract translation: 描述了用于在用作单个主板的共面板之间互连和分配信号和功率的系统，方法和主板组件。 主板组件包括具有相对的平行的第一和第二表面的多层第一印刷电路板，每个具有设置在其上的至少一个焊盘格栅阵列（LGA）。 组件还包括至少一个布线层（Y），其被设计成仅电连接第一PCB上或其内部的部件，以及至少一个布线层（X），其设计成仅将第一PCB上的部件电连接到多层第二PCB 。 所述多层第二PCB具有相对的平行的第一和第二表面，所述第一表面具有设置在其上的至少一个LGA。 它还包括至少一个被设计成仅电连接第二PCB上或第二PCB内的组件的布线层（V），以及设计成仅将第二PCB上的部件与第一PCB上的部件电互连的至少一个层（X） 。 第一LGA插入器耦合到布置在第一PCB的第一表面上的LGA，并且将至少一个部件电连接到第一PCB。 第二LGA插入件夹在布置在第一PCB的第二表面上的LGA之间并耦合到布置在第二PCB的第一表面上的LGA。 它将第一个PCB电连接到第二个PCB上的组件。

公开(公告)号：US07904849B2

公开(公告)日：2011-03-08

申请号：US11951705

申请日：2007-12-06

Applicant: Anand Haridass ,  Andreas Huber ,  Bao G. Truong ,  Roger D. Weekly

Inventor： Anand Haridass ,  Andreas Huber ,  Bao G. Truong ,  Roger D. Weekly

IPC: G06F17/50 ,  G06F9/45

CPC classification number: H01L23/50 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  Y10T29/49155 ,  Y10T29/49163 ,  H01L2924/00

Abstract: A mechanism for reducing the vertical cross-talk interference experienced in signal lines due to the inductive affects from signal lines in other signal planes of a multi-layer ceramic package is provided. With the apparatus and method, one or more vias in the multi-layer ceramic package may be removed from the structure to provide area through which an offset of the signal lines may pass. Because these offsets of the signal lines exist in parallel planes above or below each other, with no ground lines existing directly between these signal line offsets, a capacitive cross-talk is introduced into the signal lines. This capacitive cross-talk is opposite in polarity to the inductive cross-talk already experienced by the signal lines. As a result, the capacitive cross-talk tends to negate or reduce the inductive cross-talk thereby reducing the far end noise in the signal line.

Abstract translation: 提供了一种用于减少由于来自多层陶瓷封装的其它信号面中的信号线的感应影响而在信号线中遭受的垂直串扰干扰的机制。 利用该装置和方法，多层陶瓷封装中的一个或多个通孔可以从结构中移除以提供信号线的偏移通过的区域。 由于信号线的这些偏移存在于彼此之上或之下的并行平面中，在这些信号线偏移之间没有直接存在接地线，所以在信号线中引入电容性串扰。 该电容串扰与信号线已经经历的电感串扰的极性相反。 结果，电容串扰倾向于消除或减少电感串扰，从而减少信号线中的远端噪声。

公开(公告)号：US20100035426A1

公开(公告)日：2010-02-11

申请号：US12579517

申请日：2009-10-15

Applicant: Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

Inventor： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

IPC: H01L21/768 ,  G06F17/50

CPC classification number: H01L21/76879 ,  H01L23/66 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/3011 ,  H05K1/0253 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/0969 ,  H01L2224/0401

Abstract: An integrated circuit substrate is designed and fabricated with a selectively applied transmission line reference plane metal layer to achieve signal path shielding and isolation, while avoiding drops in impedance due to capacitance between large diameter vias and the transmission line reference plane metal layer. The transmission line reference plane defines voids above (or below) the signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. For voltage-plane bearing PTHs, no voids are introduced, so that signal path conductors can be routed above or adjacent to the voltage-plane bearing PTHs, with the transmission line reference plane preventing shunt capacitance between the signal path conductors and the PTHs.

Abstract translation: 集成电路衬底被设计和制造，具有选择性地施加的传输线参考平面金属层，以实现信号路径屏蔽和隔离，同时避免由于大直径通孔和传输线参考平面金属层之间的电容引起的阻抗下降。 传输线参考平面定义穿过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会由于并联电容引起的阻抗失配而降级 从信号承载PTH的顶部（或底部）到传输线参考平面。 对于电压平面轴承PTH，不引入空隙，使得信号路径导体可以路由在电压平面轴承PTH上方或附近，传输线参考平面防止信号路径导体和PTH之间的分流电容。

公开(公告)号：US07646082B2

公开(公告)日：2010-01-12

申请号：US11751786

申请日：2007-05-22

Applicant: Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

Inventor： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

IPC: H01L29/40 ,  H01L29/73 ,  H01L23/52

CPC classification number: H01L21/76879 ,  H01L23/66 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/3011 ,  H05K1/0253 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/0969 ,  H01L2224/0401

Abstract: A multi-layer circuit substrate and method having improved transmission line integrity and increased routing density uses a selectively applied transmission line reference plane metal layer to achieve signal path shielding and isolation, while avoiding drops in impedance due to capacitance between large diameter vias and the transmission line reference plane metal layer. The transmission line reference plane defines voids above (or below) the signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. For voltage-plane bearing PTHs, no voids are introduced, so that signal path conductors can be routed above or adjacent to the voltage-plane bearing PTHs, with the transmission line reference plane preventing shunt capacitance between the signal path conductors and the PTHs.

Abstract translation: 具有改进的传输线完整性和增加的布线密度的多层电路基板和方法使用选择性地施加的传输线参考平面金属层来实现信号路径屏蔽和隔离，同时避免由于大直径通孔和传输之间的电容引起的阻抗下降 线参考平面金属层。 传输线参考平面定义穿过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会由于并联电容引起的阻抗失配而降级 从信号承载PTH的顶部（或底部）到传输线参考平面。 对于电压平面轴承PTH，不引入空隙，使得信号路径导体可以路由在电压平面轴承PTH上方或附近，传输线参考平面防止信号路径导体和PTH之间的分流电容。

公开(公告)号：US20090063065A1

公开(公告)日：2009-03-05

申请号：US11848380

申请日：2007-08-31

Applicant: Roger D. Weekly

Inventor： Roger D. Weekly

IPC: G06F19/00

CPC classification number: G06F1/3203 ,  G06F1/28 ,  G06F1/305 ,  G06F1/3237 ,  Y02D10/128

Abstract: A method and system for applying multiple voltage droop detection and instruction throttling instances with customized thresholds across semiconductor chips. Environmental parameters are detected for various locations on a chip, and timing margins are determined for each location on the chip. An acceptable voltage droop for each location is determined based on the environmental parameters and the timing margins for the corresponding location. A droop threshold is then determined for each location based on the corresponding acceptable voltage droop determined for the corresponding location.

Abstract translation: 一种用于跨半导体芯片应用具有定制阈值的多个电压下降检测和指令调节实例的方法和系统。 检测芯片上各个位置的环境参数，并为芯片上的每个位置确定定时裕度。 基于相应位置的环境参数和定时裕度来确定每个位置的可接受电压下降。 然后基于为相应位置确定的相应的可接受电压下降，为每个位置确定下垂阈值。

公开(公告)号：US20080295041A1

公开(公告)日：2008-11-27

申请号：US11753644

申请日：2007-05-25

Applicant: Tingdong Zhou ,  Michael A. Christo ,  Julio A. Maldonado ,  Roger D. Weekly

Inventor： Tingdong Zhou ,  Michael A. Christo ,  Julio A. Maldonado ,  Roger D. Weekly

IPC: G06F17/50

CPC classification number: H05K1/0262 ,  G06F17/5068 ,  G06F2217/78 ,  H05K3/0005 ,  H05K2201/093 ,  H05K2201/09336 ,  H05K2201/09345 ,  H05K2201/09663

Abstract: A method for electronic circuit power plane design includes analyzing direct current (DC) properties of a power plane of an electronic circuit. The method includes analyzing power net inductance (PNI) properties of the power plane and identifying victim areas of the power plane having predetermined current density properties based on the DC properties and the PNI properties of the power plane. The method further includes replacing the identified victim areas with ground (GND) shapes to form a modified power plane.

Abstract translation: 一种用于电子电路电源平面设计的方法包括分析电子电路的电源平面的直流（DC）特性。 该方法包括基于电力平面的DC特性和PNI特性来分析功率平面的功率网络电感（PNI）特性和识别具有预定电流密度特性的功率平面的受害区域。 该方法还包括用地（GND）形状替换所识别的受害区域，以形成修改后的电力平面。

公开(公告)号：US07430800B2

公开(公告)日：2008-10-07

申请号：US11146441

申请日：2005-06-06

Applicant: Anand Haridass ,  Andreas Huber ,  Bao G. Truong ,  Roger D. Weekly

Inventor： Anand Haridass ,  Andreas Huber ,  Bao G. Truong ,  Roger D. Weekly

IPC: H05K3/02 ,  H05K3/10

CPC classification number: H01L23/50 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  Y10T29/49155 ,  Y10T29/49163 ,  H01L2924/00

Abstract: A mechanism for reducing the vertical cross-talk interference experienced in signal lines due to the inductive affects from signal lines in other signal planes of a multi-layer ceramic package is provided. With the apparatus and method, one or more vias in the multi-layer ceramic package may be removed from the structure to provide area through which an offset of the signal lines may pass. Because these offsets of the signal lines exist in parallel planes above or below each other, with no ground lines existing directly between these signal line offsets, a capacitive cross-talk is introduced into the signal lines. This capacitive cross-talk is opposite in polarity to the inductive cross-talk already experienced by the signal lines. As a result, the capacitive cross-talk tends to negate or reduce the inductive cross-talk thereby reducing the far end noise in the signal line.

Abstract translation: 提供了一种用于减少由于来自多层陶瓷封装的其它信号面中的信号线的感应影响而在信号线中遭受的垂直串扰干扰的机制。 利用该装置和方法，多层陶瓷封装中的一个或多个通孔可以从结构中移除以提供信号线的偏移通过的区域。 由于信号线的这些偏移存在于彼此之上或之下的并行平面中，在这些信号线偏移之间没有直接存在接地线，所以在信号线中引入电容性串扰。 该电容串扰与信号线已经经历的电感串扰的极性相反。 结果，电容串扰倾向于消除或减少电感串扰，从而减少信号线中的远端噪声。

公开(公告)号：US08624297B2

公开(公告)日：2014-01-07

申请号：US12579517

申请日：2009-10-15

Applicant: Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

Inventor： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

IPC: H01L27/10 ,  H01L21/4763

CPC classification number: H01L21/76879 ,  H01L23/66 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/3011 ,  H05K1/0253 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/0969 ,  H01L2224/0401

Abstract: An integrated circuit substrate is designed and fabricated with a selectively applied transmission line reference plane metal layer to achieve signal path shielding and isolation, while avoiding drops in impedance due to capacitance between large diameter vias and the transmission line reference plane metal layer. The transmission line reference plane defines voids above (or below) the signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. For voltage-plane bearing PTHs, no voids are introduced, so that signal path conductors can be routed above or adjacent to the voltage-plane bearing PTHs, with the transmission line reference plane preventing shunt capacitance between the signal path conductors and the PTHs.

Abstract translation: 集成电路衬底被设计和制造，具有选择性地施加的传输线参考平面金属层，以实现信号路径屏蔽和隔离，同时避免由于大直径通孔和传输线参考平面金属层之间的电容引起的阻抗下降。 传输线参考平面定义穿过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会由于并联电容引起的阻抗失配而降级 从信号承载PTH的顶部（或底部）到传输线参考平面。 对于电压平面轴承PTH，不引入空隙，使得信号路径导体可以路由在电压平面轴承PTH上方或附近，传输线参考平面防止信号路径导体和PTH之间的分流电容。

公开(公告)号：US08619432B2

公开(公告)日：2013-12-31

申请号：US12895251

申请日：2010-09-30

Applicant: Douglas A. Baska ,  Daniel M. Dreps ,  Rohan U. Mandrekar ,  Roger D. Weekly

Inventor： Douglas A. Baska ,  Daniel M. Dreps ,  Rohan U. Mandrekar ,  Roger D. Weekly

IPC: H01R9/00

CPC classification number: H05K3/4623 ,  H05K1/0216 ,  H05K1/141 ,  H05K3/368 ,  H05K2201/10189 ,  Y10T29/49126 ,  Y10T29/49162 ,  Y10T29/53004

Abstract: Some embodiments of the inventive subject matter are directed to a first circuit board configured to include an electronic component. The electronic component includes a plurality of leads. The first circuit board includes first wires configured to connect to a first portion of the plurality of leads. The second circuit board is affixed to the first circuit board. The second circuit board includes second wires. The second circuit board is smaller in size than the first circuit board. A plurality of electrical connectors extend through a thickness of the first circuit board and are configured to connect a second portion of the plurality of leads to the second wires.

Abstract translation: 本发明的一些实施例涉及被配置为包括电子部件的第一电路板。 电子部件包括多个引线。 第一电路板包括被配置为连接到多个引线的第一部分的第一布线。 第二电路板固定在第一电路板上。 第二电路板包括第二导线。 第二个电路板的尺寸比第一个电路板小。 多个电连接器延伸穿过第一电路板的厚度，并且被配置为将多个引线的第二部分连接到第二导线。