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公开(公告)号：US20180088856A1
公开(公告)日：2018-03-29
申请号：US15696443
申请日：2017-09-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Geun Yeong YU , Beom Kyu Shin , Myung Kyu Lee , Jun Jin Kong , Hong Rak Son
IPC: G06F3/06
CPC classification number: G06F3/0644 , G06F3/0604 , G06F3/0614 , G06F3/0647 , G06F3/0688 , G06F3/0689
Abstract: A data storage system that provides improved reliability and performance comprises a first memory device including a plurality of first storage components and a first memory controller, the first memory controller controls operation of the first storage components, a second memory device including a plurality of second storage components and a second memory controller, the second memory controller controls operation of the second storage components, a grading device determining grades for each of the first storage components and the second storage components, and a system controller that the location of data based on the grades of the first storage components and the second storage components.
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12.发明授权公开(公告)号：US09672147B2
公开(公告)日：2017-06-06
申请号：US14014511
申请日：2013-08-30
Inventor： Hye Jeong So , Sae Young Chung , Jun Jin Kong , Chang Kyu Seol
CPC classification number: G06F12/0246 , G06F3/0659 , G06F2212/1036 , G06F2212/7202 , G06F2212/7204
Abstract: A memory controller controls operation of a nonvolatile memory device comprising a memory area comprising a plurality of multi-level cells (MLCs). The memory controller receives an address of the memory area and data to be programmed to the memory area, analyzes access history information regarding the memory area based on the address, generates first mapping data corresponding to the data or second mapping data based on the data and previous mapping data that has been programmed to the MLCs according to a result of the analysis, and transmits a program command comprising one of the first mapping data and the second mapping data to the nonvolatile memory device.
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公开(公告)号：US09621188B2
公开(公告)日：2017-04-11
申请号：US14215659
申请日：2014-03-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Eran Hof , Jun Jin Kong
CPC classification number: H03M13/1108 , H03M13/1111 , H03M13/1515 , H03M13/152 , H03M13/19 , H03M13/2957 , H03M13/3707
Abstract: A decoder unit is configured to perform a decoding on encoded data. The decoder unit includes a data bus comprising a number N of data lines, a local memory configured to store messages for a message-passing decoding and communicate the messages across the data bus, a plurality of first decoder processing units, wherein each first decoder processing unit is configured to perform the message-passing decoding by communicating with the local memory using a number A of the data channels, and a plurality of second decoder processing units, where each second decoder processing unit is configured to perform the message-passing decoding by communicating with the local memory using a number B of the data lines. N is at least two, A and B are less than or equal to N, and A is different from B.
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公开(公告)号：US09483413B2
公开(公告)日：2016-11-01
申请号：US14523159
申请日：2014-10-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Avner Dor , Elona Erez , Shay Landis , Jun Jin Kong
IPC: G06F12/10
CPC classification number: G06F12/1009 , G06F12/0246 , G06F2212/152 , G06F2212/2022 , G06F2212/7201 , G06F2212/7203
Abstract: At least one example embodiment discloses a method of controlling a nonvolatile memory device including a plurality of blocks, each block including a plurality of physical pages. The method includes receiving a plurality of logical pages associated with a first plurality of logical addresses, respectively, and writing the first plurality of logical pages to the plurality physical addresses according to an ascending order of the logical addresses of the first plurality of logical pages.
Abstract translation: 至少一个示例性实施例公开了一种控制包括多个块的非易失性存储器件的方法，每个块包括多个物理页。 该方法包括分别接收与第一多个逻辑地址相关联的多个逻辑页面，并根据第一多个逻辑页面的逻辑地址的升序将多个逻辑页面写入多个物理地址。
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公开(公告)号：US11681579B2
公开(公告)日：2023-06-20
申请号：US17344180
申请日：2021-06-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dae-Hyun Kim , Yong-Gyu Chu , Jun Jin Kong , Ki-Jun Lee , Myung-Kyu Lee
IPC: G06F11/10 , G11C29/52 , G06F13/16 , G11C11/401 , H01L25/065 , G11C11/4096 , G11C29/42 , G06F21/55
CPC classification number: G06F11/1068 , G06F13/1668 , G11C11/401 , G11C29/52 , H01L25/0657 , G06F11/1012 , G06F11/1032 , G06F21/554 , G11C11/4096 , G11C29/42 , H01L2225/06513 , H01L2225/06541
Abstract: A semiconductor memory device includes: a memory cell array including a plurality of memory cells; an error correction code (ECC) engine configured to detect and/or correct at least one error bit in read data and configured to generate a decoding status flag indicative of whether the at least one error bit is detected and/or corrected, wherein the read data is read from the memory cell array; a channel interface circuit configured to receive the read data and the decoding status flag from the ECC engine and configured to transmit the read data and the decoding status flag to a memory controller, wherein the channel interface circuit is configured to transmit the decoding status flag to the memory controller through a pin; and a control logic circuit configured to control the ECC engine and the channel interface circuit in response to an address and a command from the memory controller.
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Patent Agency Ranking
公开(公告)号：US11551775B2
公开(公告)日：2023-01-10
申请号：US17313236
申请日：2021-05-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sunggi Ahn , Yesin Ryu , Jun Jin Kong , Eunae Lee , Jihyun Choi
Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit and a control logic circuit to control the ECC circuit. The memory cell array includes memory cells and a normal cell region and a parity cell region The ECC circuit, in a normal mode, receives a main data, performs an ECC encoding on the main data to generate a parity data and stores the main data and the parity data in the normal cell region and the parity cell region. The ECC circuit, in a test mode, receives a test data including at least one error bit, stores the test data in one of the normal cell region and the parity cell region and performs an ECC decoding on the test data and one of the main data and the parity data to provide a decoding result data to an external device.
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公开(公告)号：US11036578B2
公开(公告)日：2021-06-15
申请号：US16217249
申请日：2018-12-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dae-Hyun Kim , Yong-Gyu Chu , Jun Jin Kong , Ki-Jun Lee , Myung-Kyu Lee
IPC: G06F11/10 , G11C29/52 , G06F13/16 , G11C11/401 , H01L25/065 , G11C11/4096 , G11C29/42 , G06F21/55
Abstract: A semiconductor memory device includes: a memory cell array including a plurality of memory cells; an error correction code (ECC) engine configured to detect and/or correct at least one error bit in read data and configured to generate a decoding status flag indicative of whether the at least one error bit is detected and/or corrected, wherein the read data is read from the memory cell array; a channel interface circuit configured to receive the read data and the decoding status flag from the ECC engine and configured to transmit the read data and the decoding status flag to a memory controller, wherein the channel interface circuit is configured to transmit the decoding status flag to the memory controller through a pin; and a control logic circuit configured to control the ECC engine and the channel interface circuit in response to an address and a command from the memory controller.
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公开(公告)号：US11016689B2
公开(公告)日：2021-05-25
申请号：US15696443
申请日：2017-09-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Geun Yeong Yu , Beom Kyu Shin , Myung Kyu Lee , Jun Jin Kong , Hong Rak Son
IPC: G06F3/06
Abstract: A data storage system that provides improved reliability and performance comprises a first memory device including a plurality of first storage components and a first memory controller, the first memory controller controls operation of the first storage components, a second memory device including a plurality of second storage components and a second memory controller, the second memory controller controls operation of the second storage components, a grading device determining grades for each of the first storage components and the second storage components, and a system controller that the location of data based on the grades of the first storage components and the second storage components.
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公开(公告)号：US10922171B2
公开(公告)日：2021-02-16
申请号：US16441287
申请日：2019-06-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sung-Hye Cho , Ki-Jun Lee , Myung-Kyu Lee , Jun Jin Kong
Abstract: An error correction code (ECC) circuit of a semiconductor memory device includes a syndrome generation circuit and a correction circuit. The syndrome generation circuit generates syndrome based on a message and first parity bits in a codeword read from a memory cell array by using one of a first parity check matrix and a second parity check matrix, in response to a decoding mode signal. The correction circuit receives the codeword, corrects at least a portion of (t1+t2) error bits in the codeword based on the syndrome and outputs a corrected message. Here, t1 and t2 are natural numbers, respectively.
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公开(公告)号：US10700714B2
公开(公告)日：2020-06-30
申请号：US16229153
申请日：2018-12-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dong Min Shin , Beom Kyu Shin , Heon Hwa Cheong , Jun Jin Kong , Hong Rak Son , Yeong Geol Song , Se Jin Lim
Abstract: A method of operating a decoder, which has variable nodes and check nodes, includes receiving variable-to-check (V2C) messages from the variable nodes using a first check node among the check nodes. The number of messages having a specific magnitude among the V2C messages is counted. The magnitude of a check-to-variable (C2V) message to be transmitted to a first variable node, among the variable nodes, is determined based on the count value and the magnitude of a V2C message of the first variable node.
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