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公开(公告)号：US20240282773A1
公开(公告)日：2024-08-22
申请号：US18645551
申请日：2024-04-25
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seokhyeon Yoon , Junyoung Park , Woocheol Shin , Seunghun Lee
IPC: H01L27/12 , H01L29/06 , H01L29/08 , H01L29/786
CPC classification number: H01L27/1203 , H01L27/1222 , H01L29/0653 , H01L29/0665 , H01L29/0847 , H01L29/78696
Abstract: An integrated circuit device includes: a semiconductor on insulator (SOI) substrate layer including a base substrate layer, an insulating substrate layer, and a cover substrate layer; a semiconductor substrate layer; a plurality of first fin-type active areas and a plurality of second fin-type active areas each defined by a plurality of trenches, and extending in a first horizontal direction, in above the SOI substrate layer and the semiconductor substrate layer, respectively; a plurality of nanosheet stacked structures comprising nanosheets extending in parallel with each other and spaced apart from upper surfaces of the plurality of first fin-type active areas and the plurality of second fin-type active areas; a plurality of first source/drain regions extending into the SOI substrate layer; and a plurality of second source/drain regions extending into the semiconductor substrate layer. Lower surfaces of the first and second source/drain regions may not be coplanar with each other.
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公开(公告)号：US11914416B2
公开(公告)日：2024-02-27
申请号：US17737575
申请日：2022-05-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Junyoung Park , Joohwan Kim , Jindo Byun , Eunseok Shin , Hyunyoon Cho , Youngdon Choi , Junghwan Choi
Abstract: A transmitter circuit that receives parallel signals and outputs a serial signal in response to the parallel signals may include; a clock generator generating first clock signals having different respective phases, a multiplexer including selection circuits respectively configured to selectively provide at least two of the parallel signals to an output node in response to at least two of the first clock signals, and an output driver generating the serial signal by amplifying a signal at the output node.
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13.发明授权公开(公告)号：US11804838B2
公开(公告)日：2023-10-31
申请号：US17751148
申请日：2022-05-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junyoung Park , Joohwan Kim , Jindo Byun , Eunseok Shin , Hyunyoon Cho , Youngdon Choi , Junghwan Choi
IPC: H03K17/693 , H03K19/20 , G11C11/4076 , G11C11/4093 , H03M9/00
CPC classification number: H03K17/693 , H03K19/20 , G11C11/4076 , G11C11/4093 , H03M9/00
Abstract: A transmitter circuit includes a clock generator configured to generate a plurality of clock signals having different phases, and a plurality of selection circuits configured to receive a plurality of parallel data signals and output a serial data signal on an output node based on the plurality of clock signals and the received plurality of parallel data signals. Each of the plurality of selection circuits includes a data multiplexer configured to generate a plurality of data selection signals based on the received one of the plurality of parallel data signals and the plurality of clock signals; a control signal generator configured to generate first and second control signals based on the plurality of data selection signals; and an output driver connected to the output node, and configured to precharge the output node based on the first control signal or discharge the output node based on the second control signal.
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公开(公告)号：US11651799B2
公开(公告)日：2023-05-16
申请号：US17323009
申请日：2021-05-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Junyoung Park , Jaewoo Park , Younghoon Son , Youngdon Choi , Junghwan Choi
CPC classification number: G11C5/147 , G11C7/109 , G11C7/1063 , G11C7/1069 , G11C7/1096 , G11C11/565 , H04L25/028 , H04L25/4917 , G11C2207/101
Abstract: A method of generating a multi-level signal having one of three or more voltage levels that are different from each other, the method including: performing a first voltage setting operation in which first and second voltage intervals are adjusted to be different from each other, wherein the first voltage interval represents a difference between a first pair of adjacent voltage levels and the second voltage interval represents a difference between a second pair of adjacent voltage levels; performing a second voltage setting operation in which a voltage swing width is adjusted, the voltage swing width representing a difference between a lowest and a highest voltage level among the three or more voltage levels; and generating an output data signal that is the multi-level signal based on input data including two or more bits, a result of the first voltage setting operation and a result of the second voltage setting operation.
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公开(公告)号：US20220059156A1
公开(公告)日：2022-02-24
申请号：US17321678
申请日：2021-05-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Junyoung Park , Younghoon Son , Hyunyoon Cho , Youngdon Choi , Junghwan Choi
IPC: G11C11/4093 , G11C11/4076 , G06F13/16
Abstract: In a method of generating a multi-level signal having one of three or more voltage levels that are different from one another, input data including two or more bits is received. A drive strength of at least one of two or more driving paths is changed based on the two or more bits such that a first transition time, during which an output data signal is transitioned from a first voltage level to a second voltage level, is changed. The output data signal that is the multi-level signal is generated such that the first transition time of the output data signal is changed and a second transition time, during which the output data signal is transitioned from the first voltage level to a third voltage level different from the second voltage level, is maintained.
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Patent Agency Ranking
公开(公告)号：US11018579B2
公开(公告)日：2021-05-25
申请号：US16678021
申请日：2019-11-08
Inventor： Seungchul Jung , Sang Joon Kim , Junyoung Park , Yoonmyung Lee , Hyungmin Gi
Abstract: A boost converter and a cell applicable to the boost converter are provided. The cell comprises a control circuit configured to generate a bottom control signal related to a bottom plate of a capacitor, and a top control signal related to a top plate of the capacitor to connect the capacitor based on one or more operational phases, and a booster configured to convert the top control signal generated by the control circuit, wherein the capacitor is configured to be sequentially connected to voltage levels through switches, based on the bottom control signal and the converted top control signal.
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公开(公告)号：US12119331B2
公开(公告)日：2024-10-15
申请号：US17677453
申请日：2022-02-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ju-Il Choi , Gyuho Kang , Heewon Kim , Sechul Park , Jongho Park , Junyoung Park
IPC: H01L23/498 , H01L23/00 , H01L23/48 , H01L23/538 , H01L25/10 , H01L25/065
CPC classification number: H01L25/105 , H01L23/481 , H01L23/49816 , H01L23/49822 , H01L23/49838 , H01L23/5383 , H01L23/5386 , H01L24/08 , H01L24/32 , H01L23/49833 , H01L24/80 , H01L25/0657 , H01L2224/08237 , H01L2224/32225 , H01L2224/80895 , H01L2225/06513 , H01L2225/06541 , H01L2225/1023 , H01L2225/1058 , H01L2225/1094 , H01L2924/1431 , H01L2924/1434
Abstract: Disclosed is a semiconductor package comprising an interposer substrate having first and second surfaces opposite each other and including a wiring layer adjacent to the first surface, a semiconductor chip on the first surface of the interposer substrate, a passivation layer on the first surface of the interposer substrate and covering the semiconductor chip, and redistribution patterns in the passivation layer and connected to the semiconductor chip. The semiconductor chip has third and fourth surfaces opposite to each other. The third surface of the semiconductor chip faces the first surface of the interposer substrate. The redistribution patterns are connected to the fourth surface of the semiconductor chip. The semiconductor chip includes chip pads adjacent to the third surface and chip through electrodes connected to the chip pads. Each of the chip pads is directly bonded to a corresponding one of wiring patterns in the wiring layer.
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公开(公告)号：US20240088094A1
公开(公告)日：2024-03-14
申请号：US18314287
申请日：2023-05-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyojin Yun , Unbyoung Kang , Seokbong Park , Sechul Park , Junyoung Park , Teahwa Jeong , Juil Choi
IPC: H01L25/065 , H01L23/00 , H01L23/31 , H01L23/498 , H01L23/538
CPC classification number: H01L25/0655 , H01L23/3157 , H01L23/49816 , H01L23/5383 , H01L23/5387 , H01L24/16 , H01L2224/16227
Abstract: A semiconductor package includes a substrate including a first region, a second region in contact with the first region with the first and second regions stacked in a first direction, and a third region extending from the first and second regions in a second direction, perpendicular to the first direction, to connect the first and second regions to each other in bent form, a first semiconductor chip on a first side opposite to a second side of the first region in contact with the second region, a second semiconductor chip on a first side opposite to a second side of the second region in contact with the first region, a first molding member on the first region and covering at least a portion of the first semiconductor chip, and a second molding member on the second region and covering at least a portion of the second semiconductor chip.
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公开(公告)号：US11791811B2
公开(公告)日：2023-10-17
申请号：US17806827
申请日：2022-06-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyunsub Rie , Eunseok Shin , Youngdon Choi , Junyoung Park , Hyunyoon Cho , Junghwan Choi
CPC classification number: H03K5/1565 , G11C7/222 , H03K3/017 , H03K5/135 , H03K2005/00241
Abstract: A delay circuit for a clock signal includes a first signal generator, a first inverting circuit, a second signal generator and a second inverting circuit. The first signal generator is configured to generate a plurality of first switching signals based on a delay code. The first inverting circuit includes a plurality of first inverters that are selectively turned on in response to the plurality of first switching signals, respectively, and is configured to adjust a first delay time for both of a first edge and a second edge of the clock signal. The second signal generator is configured to generate a plurality of second switching signals based on a duty code. The second inverting circuit includes a plurality of second pull-up units and a plurality of second pull-down units, respective ones of the plurality of second pull-up units or respective ones of the plurality of second pull-down units are selectively turned on in response to respective ones of the plurality of second switching signals. The second inverting circuit is configured to adjust a second delay time for the first edge, the second edge, or both of the first edge and the second edge of the clock signal.
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公开(公告)号：US20220208790A1
公开(公告)日：2022-06-30
申请号：US17410325
申请日：2021-08-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seokhyeon Yoon , Junyoung Park , Woocheol Shin , Seunghun Lee
IPC: H01L27/12 , H01L29/06 , H01L29/786 , H01L29/08
Abstract: An integrated circuit device includes: a semiconductor on insulator (SOI) substrate layer including a base substrate layer, an insulating substrate layer, and a cover substrate layer; a semiconductor substrate layer; a plurality of first fin-type active areas and a plurality of second fin-type active areas each defined by a plurality of trenches, and extending in a first horizontal direction, in above the SOI substrate layer and the semiconductor substrate layer, respectively; a plurality of nanosheet stacked structures comprising nanosheets extending in parallel with each other and spaced apart from upper surfaces of the plurality of first fin-type active areas and the plurality of second fin-type active areas; a plurality of first source/drain regions extending into the SOI substrate layer; and a plurality of second source/drain regions extending into the semiconductor substrate layer. Lower surfaces of the first and second source/drain regions may not be coplanar with each other.
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