公开(公告)号：US08940584B2

公开(公告)日：2015-01-27

申请号：US14272681

申请日：2014-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tongsuk Kim ,  Jangwoo Lee ,  Heeseok Lee ,  Kyoungsei Choi

IPC: H01L21/44 ,  H01L23/06 ,  H01L23/10 ,  H01L23/31 ,  H01L23/552 ,  H01L23/498 ,  H01L21/56 ,  H01L23/34 ,  H01L25/065 ,  H01L23/36 ,  H01L23/42

CPC classification number: H01L23/06 ,  H01L21/563 ,  H01L23/10 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/36 ,  H01L23/42 ,  H01L23/49816 ,  H01L23/552 ,  H01L23/562 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06568 ,  H01L2924/15311 ,  H01L2924/16172 ,  H01L2924/16251 ,  H01L2924/00

Abstract: A semiconductor package including a package substrate having a chip mounting region and a peripheral region and including a ground layer formed in the peripheral region, first solder balls on the package substrate in the chip mounting region, second solder balls on the ground layer, at least one semiconductor chip stacked on the package substrate in the chip mounting region, and a package cap covering the semiconductor chip and contacting the package substrate in the peripheral region may be provided. The package cap is electrically connected to the second solder balls. Methods of fabricating the semiconductor package are also provided.

Abstract translation: 一种半导体封装，包括具有芯片安装区域和周边区域的封装基板，并且包括形成在周边区域中的接地层，在芯片安装区域中的封装基板上的第一焊球，接地层上的第二焊球，至少 可以提供在芯片安装区域中堆叠在封装基板上的一个半导体芯片，以及覆盖半导体芯片并且在周边区域中与封装基板接触的封装帽。 封装帽电连接到第二焊球。 还提供了制造半导体封装的方法。

公开(公告)号：US12062605B2

公开(公告)日：2024-08-13

申请号：US18308433

申请日：2023-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hwang Kim ,  Hyunkyu Kim ,  Jongbo Shim ,  Eunhee Jung ,  Kyoungsei Choi

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/45 ,  H01L25/0657

Abstract: A semiconductor package includes a lower package, an interposer on the lower package, and an under-fill layer between the interposer and the lower package. The interposer includes a through hole that vertically penetrates the interposer. The under-fill layer includes an extension that fills at least a portion of the through hole.

公开(公告)号：US11658107B2

公开(公告)日：2023-05-23

申请号：US17807894

申请日：2022-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hwang Kim ,  Hyunkyu Kim ,  Jongbo Shim ,  Eunhee Jung ,  Kyoungsei Choi

IPC: H01L23/498 ,  H01L23/31 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/45 ,  H01L25/0657

Abstract: A semiconductor package includes a lower package, an interposer on the lower package, and an under-fill layer between the interposer and the lower package. The interposer includes a through hole that vertically penetrates the interposer. The under-fill layer includes an extension that fills at least a portion of the through hole.

公开(公告)号：US11581263B2

公开(公告)日：2023-02-14

申请号：US17024852

申请日：2020-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongbin Yim ,  Jungwoo Kim ,  Jihwang Kim ,  Jungsoo Byun ,  Jongbo Shim ,  Doohwan Lee ,  Kyoungsei Choi ,  Junggon Choi ,  Sungeun Pyo

IPC: H01L23/495 ,  H01L23/538 ,  H01L25/10

Abstract: A semiconductor package includes: a redistribution layer including a plurality of redistribution insulating layers, a plurality of redistribution line patterns that constitute lower wiring layers, and a plurality of redistribution vias that are connected to some of the plurality of redistribution line patterns while penetrating at least one of the plurality of redistribution insulating layers; at least one semiconductor chip arranged on the redistribution layer; an expanded layer surrounding the at least one semiconductor chip on the redistribution layer; and a cover wiring layer including at least one base insulating layer, a plurality of wiring patterns that constitute upper wiring layers, and a plurality of conductive vias that are connected to some of the plurality of wiring patterns while penetrating the at least one base insulating layer.

公开(公告)号：US11367679B2

公开(公告)日：2022-06-21

申请号：US17017638

申请日：2020-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hwang Kim ,  Hyunkyu Kim ,  Jongbo Shim ,  Eunhee Jung ,  Kyoungsei Choi

IPC: H01L23/498 ,  H01L23/31 ,  H01L25/065 ,  H01L23/00

Abstract: A semiconductor package includes a lower package, an interposer on the lower package, and an under-fill layer between the interposer and the lower package. The interposer includes a through hole that vertically penetrates the interposer. The under-fill layer includes an extension that fills at least a portion of the through hole.

公开(公告)号：US10825776B2

公开(公告)日：2020-11-03

申请号：US16240174

申请日：2019-01-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoonha Jung ,  Jongkook Kim ,  Bona Baek ,  Heeseok Lee ,  Kyoungsei Choi

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10 ,  H01L23/552 ,  H01L23/31

Abstract: A semiconductor package includes a first plate having a through hole therein, at least one interconnection layer disposed on a first surface of the first plate, and at least one semiconductor chip disposed on the at least one interconnection layer in a space defined by the through hole and electrically connected to the least one interconnection layer. The package further includes a second plate disposed on the at least one semiconductor chip and a second surface of the first plate on a side of the first plate opposite the first surface, and at least one conductive pad disposed on the second surface of the first plate and electrically connected to the at least one interconnection layer.

公开(公告)号：US20190074316A1

公开(公告)日：2019-03-07

申请号：US16177780

申请日：2018-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Un-Byoung KANG ,  Yungcheol Kong ,  Hyunsu Jun ,  Kyoungsei Choi

IPC: H01L27/146 ,  H01L31/024 ,  H01L31/0203 ,  H01L23/00

Abstract: A semiconductor package including a substrate, a memory chip on the substrate, a mold layer on the substrate to cover a side surface of the memory chip, an image sensor chip on the memory chip and the mold layer, and a connection terminal between and electrically connecting the memory chip to the image sensor chip may be provided.

公开(公告)号：US11798889B2

公开(公告)日：2023-10-24

申请号：US17835768

申请日：2022-06-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Choongbin Yim ,  Jungwoo Kim ,  Jihwang Kim ,  Jongbo Shim ,  Kyoungsei Choi

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/14

CPC classification number: H01L23/5384 ,  H01L23/14 ,  H01L23/31 ,  H01L23/5385 ,  H01L23/5386

Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a molding layer covering side walls of the first semiconductor chip and including through holes, an interposer on the first semiconductor chip and the molding layer, conductive connectors in the through holes of the molding layer and connected to the first package substrate and the interposer, and an insulating filler including a first portion that fills the through holes of the molding layer so as to surround side walls of the conductive connectors.

公开(公告)号：US11482554B2

公开(公告)日：2022-10-25

申请号：US16898610

申请日：2020-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Un-Byoung Kang ,  Yungcheol Kong ,  Hyunsu Jun ,  Kyoungsei Choi

IPC: H01L27/146 ,  H01L31/0203 ,  H01L23/00 ,  H01L31/024

Abstract: A semiconductor package including a substrate, a memory chip on the substrate, a mold layer on the substrate to cover a side surface of the memory chip, an image sensor chip on the memory chip and the mold layer, and a connection terminal between and electrically connecting the memory chip to the image sensor chip may be provided.

公开(公告)号：US20210183777A1

公开(公告)日：2021-06-17

申请号：US17090502

申请日：2020-11-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Choongbin Yim ,  Jungwoo KIM ,  Jihwang Kim ,  Jongbo Shim ,  Kyoungsei Choi

IPC: H01L23/538 ,  H01L23/14 ,  H01L23/31

Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a molding layer covering side walls of the first semiconductor chip and including through holes, an interposer on the first semiconductor chip and the molding layer, conductive connectors in the through holes of the molding layer and connected to the first package substrate and the interposer, and an insulating filler including a first portion that fills the through holes of the molding layer so as to surround side walls of the conductive connectors.