公开(公告)号：US20230246084A1

公开(公告)日：2023-08-03

申请号：US17587470

申请日：2022-01-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA ,  Koichi MATSUNO

IPC: H01L29/423 ,  H01L21/28 ,  H01L27/11582

CPC classification number: H01L29/4234 ,  H01L29/40117 ,  H01L27/11582

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel, a memory film in contact with the vertical semiconductor channel, and a vertical stack of tubular dielectric spacers laterally surrounding the memory film. The tubular dielectric spacers may include tubular graded silicon oxynitride portions having a composition gradient such that an atomic concentration of nitrogen decreases with a lateral distance from an outer sidewall of the memory film, or may include tubular composite dielectric spacers including a respective tubular silicon oxide spacer and a respective tubular dielectric metal oxide spacer. Each of the electrically conductive layers has a hammerhead-shaped vertical cross-sectional profile.

公开(公告)号：US20230232634A1

公开(公告)日：2023-07-20

申请号：US17578199

申请日：2022-01-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA ,  Kartik SONDHI

IPC: H01L27/11597 ,  H01L29/78 ,  H01L29/66 ,  H01L29/20 ,  H01L23/48

CPC classification number: H01L27/11597 ,  H01L29/78391 ,  H01L29/6684 ,  H01L29/2003 ,  H01L23/481

Abstract: A semiconductor structure includes an active region including a source region, a drain region, and a channel region extending between the source region and the drain region, a gate stack, and a gate dielectric layer located between the gate stack and the active region. The gate stack includes an electrically conductive gate electrode and a single crystalline III-nitride ferroelectric plate located between the electrically conductive gate electrode and the gate dielectric layer, and an entirety of the single crystalline III-nitride ferroelectric plate is single crystalline.

公开(公告)号：US20230231029A1

公开(公告)日：2023-07-20

申请号：US17578177

申请日：2022-01-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA ,  Kartik SONDHI

IPC: H01L29/51 ,  H01L27/1159 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L29/516 ,  H01L27/1159 ,  H01L29/78391 ,  H01L29/40111 ,  H01L29/6684

Abstract: A semiconductor structure includes an active region including a source region, a drain region, and a channel region extending between the source region and the drain region, a gate stack, and a gate dielectric layer located between the gate stack and the active region. The gate stack includes an electrically conductive gate electrode and a single crystalline III-nitride ferroelectric plate located between the electrically conductive gate electrode and the gate dielectric layer, and an entirety of the single crystalline III-nitride ferroelectric plate is single crystalline.

公开(公告)号：US20220399350A1

公开(公告)日：2022-12-15

申请号：US17345831

申请日：2021-06-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Fei ZHOU ,  Adarsh RAJASHEKHAR

IPC: H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11565

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located within the memory openings. Each of the electrically conductive layers includes a metallic fill material layer and a plurality of vertical tubular metallic liners laterally surrounding a respective one of the memory opening fill structures and located between the metallic fill material layer and a respective one of the memory opening fill structures. The tubular metallic liners may be formed by selective metal or metal oxide deposition, or by conversion of surface portions of the metallic fill material layers into metallic compound material portions by nitridation, oxidation, or incorporation of boron atoms.

公开(公告)号：US20210296284A1

公开(公告)日：2021-09-23

申请号：US16825304

申请日：2020-03-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Adarsh RAJASHEKHAR ,  Senaka KANAKAMEDALA ,  Fei ZHOU

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

Abstract: A first semiconductor die includes first semiconductor devices located over a first substrate, first interconnect-level dielectric material layers embedding first metal interconnect structures and located on the first semiconductor devices, and a first pad-level dielectric layer located on the first interconnect-level dielectric material layers and embedding first bonding pads. Each of the first bonding pads includes a first proximal horizontal surface and at least one first distal horizontal surface that is more distal from the first substrate than the first proximal horizontal surface is from the first substrate and has a lesser total area than a total area of the first proximal horizontal surface. A second semiconductor die including second bonding pads that are embedded in a second pad-level dielectric layer can be bonded to a respective distal surface of the first bonding pads.

公开(公告)号：US20210242241A1

公开(公告)日：2021-08-05

申请号：US17237447

申请日：2021-04-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA ,  Rahul SHARANGPANI

IPC: H01L27/11597 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/76

Abstract: A three-dimensional memory device includes an alternating stack of source layers and drain layers located over a substrate, a memory opening vertically extending through the alternating stack, a vertical word line located in the memory opening and vertically extending through each of the source layers and the drain layers of the alternating stack, discrete semiconductor channels contacting horizontal surfaces of a respective vertically neighboring pair of a source layer of the source layers and a drain layer of the drain layers, and a vertical stack of discrete memory material portions laterally surrounding the vertical word line.

公开(公告)号：US20190287982A1

公开(公告)日：2019-09-19

申请号：US16020088

申请日：2018-06-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tatsuya HINOUE ,  Tomoyuki OBU ,  Tomohiro UNO ,  Yusuke MUKAE ,  Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Fei ZHOU ,  Adarsh RAJASHEKHAR

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11529 ,  H01L27/11573

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate and memory stack structures extending through the alternating stack. Each of the electrically conductive layers includes a stack of a compositionally graded diffusion barrier and a metal fill material portion, and the compositionally graded diffusion barrier includes a substantially amorphous region contacting the interface between the compositionally graded diffusion barrier and a substantially crystalline region that is spaced from the interface by the amorphous region. The substantially crystalline region effectively blocks atomic diffusion, and the amorphous region induces formation of large grains during deposition of the metal fill material portions.

公开(公告)号：US20240121960A1

公开(公告)日：2024-04-11

申请号：US18348702

申请日：2023-07-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA ,  Fei ZHOU ,  Rahul SHARANGPANI ,  Kartik SONDHI

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack and having a lateral undulation in a vertical cross-sectional profile such that the memory opening laterally protrudes outward at levels of the electrically conductive layers, and a memory opening fill structure located in the memory opening and including a vertical stack of blocking dielectric material portions located at the levels of the electrically conductive layers, a vertical stack of discrete memory elements located at the levels of the electrically conductive layers and including a respective contoured charge storage material portion, a tunneling dielectric layer overlying the contoured inner sidewalls of the tubular charge storage material portion, and a vertical semiconductor channel.

公开(公告)号：US20240064991A1

公开(公告)日：2024-02-22

申请号：US17820997

申请日：2022-08-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kartik SONDHI ,  Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Tiffany SANTOS ,  Fei ZHOU ,  Joyeeta NAG ,  Bhagwati PRASAD ,  Adarsh RAJASHEKHAR

IPC: H01L27/11597 ,  H01L27/1159

CPC classification number: H01L27/11597 ,  H01L27/1159

Abstract: A semiconductor memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical stack of discrete ferroelectric material portions and a vertical semiconductor channel. In one embodiment, the discrete ferroelectric material portions include a ferroelectric alloy material of a first dielectric metal oxide material and a second dielectric metal oxide material. In another embodiment, each of the discrete ferroelectric material portions is oxygen-deficient.

公开(公告)号：US20230345719A1

公开(公告)日：2023-10-26

申请号：US17659902

申请日：2022-04-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kartik SONDHI ,  Adarsh RAJASHEKHAR ,  Rahul SHARANGPANI ,  Raghuveer S. MAKALA

IPC: H01L27/11582 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L27/11556

Abstract: An alternating stack of insulating layers and electrically conductive layers is formed over a substrate, and a memory opening vertically extends through the alternating stack. The memory opening is laterally expanded at levels of the insulating layers. At least one blocking dielectric layer is formed in the memory opening. A first vertical stack of discrete charge storage elements is formed at levels of the electrically conductive layers. A second vertical stack of discrete dielectric material portions is formed at the levels of the insulating layers. A tunneling dielectric layer is formed over the first vertical stack and the second vertical stack. A vertical semiconductor channel is formed on the tunneling dielectric layer.