公开(公告)号：US20200265899A1

公开(公告)日：2020-08-20

申请号：US16866155

申请日：2020-05-04

Applicant: SanDisk Technologies LLC

Inventor： Kenneth Louie ,  Anirudh Amarnath

IPC: G11C16/24 ,  G11C16/26 ,  G11C16/34 ,  G11C16/30 ,  G11C16/08

Abstract: A memory device and associated techniques improve a settling time of bit lines in a memory device during a sensing operation, such as read or verify operation. Supply voltage from power supply terminals in the sense circuits is briefly toggled during a discharge of a selected bit line in response to a voltage on a selected word line being increased to a second word line level or higher. This helps to create an electrical path from the selected bit line through to a supply terminal for discharging the selected bit line such that a settling time of a voltage of the selected bit line is shortened in association with a target memory cell transitioning from a non-conductive state to a conductive state.

公开(公告)号：US20180366178A1

公开(公告)日：2018-12-20

申请号：US15627947

申请日：2017-06-20

Applicant: SanDisk Technologies LLC

Inventor： Anirudh Amarnath ,  Tai-Yuan Tseng

IPC: G11C11/4091 ,  G11C11/4094

CPC classification number: G11C11/4091 ,  G11C7/06 ,  G11C7/062 ,  G11C7/08 ,  G11C7/12 ,  G11C11/24 ,  G11C11/4094 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32 ,  G11C2211/5642

Abstract: A circuit includes selected sense circuits configured to be connected to selected bit lines and unselected sense circuits configured to be connected to unselected bit lines during a sense operation. A voltage supply circuit may supply a selected pulse and an unselected pulse to the selected and unselected sense circuits. The selected sense circuits may pass the selected pulse to associated charge-storing circuits, and reject the unselected pulse. The unselected sense circuits may pass the unselected pulse to associated charge-storing circuits, and reject the selected pulse. In addition, voltage-setting circuitry may set sense voltages in the unselected sense circuits to a pre-sense level that matches the pre-sense level of communication voltages in the unselected sense circuits.

公开(公告)号：US20220399062A1

公开(公告)日：2022-12-15

申请号：US17343075

申请日：2021-06-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Anirudh Amarnath ,  Jongyeon Kim

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/04

Abstract: A method of verifying the programming of a plurality of memory cells in a data storage system includes performing a setup operation including settling of bit lines associated with the subset of memory cells; performing a sensing operation including subjecting the settled bit lines to a verify voltage signal; and performing first and second latching operations identifying memory cells of the subset of memory cells having threshold voltages that meet first and second verify reference voltages, where the first and second latching operations are part of the same program verify operation with no setup time between them.

公开(公告)号：US20180374518A1

公开(公告)日：2018-12-27

申请号：US15630079

申请日：2017-06-22

Applicant: SanDisk Technologies LLC

Inventor： Tai-Yuan Tseng ,  Anirudh Amarnath

IPC: G11C7/08 ,  G11C11/16 ,  G11C13/00

CPC classification number: G11C7/08 ,  G11C7/12 ,  G11C11/1673 ,  G11C11/5628 ,  G11C11/5642 ,  G11C13/004 ,  G11C13/0064 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3459 ,  G11C2013/0042 ,  G11C2213/71

Abstract: A sense circuit is provided in which the threshold voltage of a memory cell is sensed relative to two different levels using a single control gate voltage on the memory cell. These two levels can be lower and higher verify voltages of a data state in a programming operation, or two read levels of a read operation. A sense node is charged up to a peak level by a pre-charge voltage and by capacitive coupling. The sense node then discharges into the bit line. The sense node voltage is decreased first and second times by capacitive coupling after which first and second bits of data are output based on a level of the sense node. The first and second bits indicate a level of the sense node relative to the lower and higher verify voltages, respectively.

公开(公告)号：US10115440B2

公开(公告)日：2018-10-30

申请号：US15625848

申请日：2017-06-16

Applicant: SanDisk Technologies LLC

Inventor： Qui Nguyen ,  Alexander Chu ,  Kenneth Louie ,  Anirudh Amarnath ,  Jixin Yu ,  Yen-Lung Jason Li ,  Tai-Yuan Tseng ,  Jong Yuh

IPC: G11C8/08 ,  G11C5/06 ,  H01L27/112 ,  G11C8/10 ,  G06F13/40

Abstract: Apparatuses, systems, and methods are disclosed for three-dimensional non-volatile memory. A stack of word line layers includes word lines for a three-dimensional non-volatile memory array. A stack of word line layers may include a plurality of tiers. Word line switch transistors transfer word line bias voltages to the word lines. Word line contact regions couple word line switch transistors to word lines. A word line contact region includes a stepped structure for a tier of word line layers. A level region separates a word line contact region for a first tier from a word line contact region for a second tier.

公开(公告)号：US10037810B1

公开(公告)日：2018-07-31

申请号：US15634006

申请日：2017-06-27

Applicant: SanDisk Technologies LLC

Inventor： Hemant Shukla ,  Saurabh Kumar Singh ,  Sridhar Yadala ,  Raul-Adrian Cernea ,  Anirudh Amarnath

IPC: G11C16/04 ,  G11C16/30 ,  G11C16/10 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C16/30 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32

Abstract: The peak voltage at which a voltage-setting transistor is driven is reduced while the body effect of the transistor is also compensated. The voltage-setting transistor is driven at an initial level and then coupled higher by a capacitor which is connected to the control gate of the voltage-setting transistor. The amount of coupling can vary as a function of an assigned data state of a memory cell connected to the transistor by a source line and/or bit line. The capacitor may have a body which is common to a set of memory cells. The voltage can be set prior to applying a program voltage to the control gate of a memory cell to control a programming speed of the memory cell based on its assigned data state. The voltage can also be set in connection with a sensing operation.

公开(公告)号：US09754645B2

公开(公告)日：2017-09-05

申请号：US14924498

申请日：2015-10-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Anirudh Amarnath ,  Tai-Yuan Tseng

IPC: G11C7/00 ,  G11C7/12

CPC classification number: G11C7/12 ,  G11C7/02 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24

Abstract: An apparatus includes a first bit line coupled to a first storage element and a second bit line coupled to a second storage element. A first bit line charging circuit is coupled to the first bit line and is configured to charge the first bit line to a first bias voltage of multiple bias voltages based on a first programming state. A second bit line charging circuit is coupled to the second bit line and is configured to charge the second bit line to a second bias voltage of the multiple bias voltages based on a second programming state. The second programming state is different than the first programming state.