公开(公告)号：US10706919B2

公开(公告)日：2020-07-07

申请号：US16268726

申请日：2019-02-06

Applicant: Toshiba Memory Corporation ,  SanDisk Technologies LLC

Inventor： Tomoharu Tanaka ,  Jian Chen

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/34 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  G11C16/12 ,  G11C16/10

Abstract: A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.

公开(公告)号：US10665313B1

公开(公告)日：2020-05-26

申请号：US16402151

申请日：2019-05-02

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Henry Chin ,  Jian Chen

IPC: G11C29/00 ,  G11C29/02 ,  G11C16/14 ,  G11C16/26 ,  G11C16/04 ,  G11C29/38 ,  G11C16/34 ,  G11C29/12

Abstract: Techniques are described for detecting a short circuit between a word line and a source line in a memory device, and to a method for recovering from such a short circuit. In one aspect, the short circuit is detected in a program operation when a selected word line completes programming after an unusually low number of program loops. A further check is performed to confirm that there is a short circuit. The short circuited word line is then erased and a recovery read is performed for previously-programmed word lines. In another aspect, a short circuit is detected in a read operation.

公开(公告)号：US20180033798A1

公开(公告)日：2018-02-01

申请号：US15445409

申请日：2017-02-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish Baraskar ,  Raghuveer S. Makala ,  Ching-Huang Lu ,  Yao-Sheng Lee ,  Jian Chen

IPC: H01L27/11582 ,  H01L21/768 ,  H01L21/28 ,  H01L23/532 ,  H01L27/11565 ,  H01L23/528 ,  H01L21/02

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/768 ,  H01L23/528 ,  H01L23/53257 ,  H01L27/11565 ,  H01L29/40117 ,  H01L29/7926

Abstract: A three-dimensional non-volatile memory comprises a plurality of word line layers arranged alternatingly with a plurality of dielectric layers in a stack over a substrate. Higher word lines are implemented to be thicker than lower word lines in order to reduce variation in resistance among word lines.

公开(公告)号：US09672916B2

公开(公告)日：2017-06-06

申请号：US15083224

申请日：2016-03-28

Applicant: SANDISK TECHNOLOGIES, LLC

Inventor： Yanli Zhang ,  George Samachisa ,  Johann Alsmeier ,  Jian Chen

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  G11C11/56

CPC classification number: G11C16/0483 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/26

Abstract: Methods for performing memory operations on a memory array that includes inverted NAND strings are described. The memory operations may include erase operations, read operations, programming operations, program verify operations, and erase verify operations. An inverted NAND string may include a string of inverted floating gate transistors or a string of inverted charge trap transistors. In one embodiment, an inverted floating gate transistor may include a tunneling layer between a floating gate of the inverted floating gate transistor and a control gate of the inverted floating gate transistor. The arrangement of the tunneling layer between the floating gate and the control gate allows electrons to be added to or removed from the floating gate via F-N tunneling between the floating gate and the control gate. The inverted NAND string may be formed above a substrate and oriented such that the inverted NAND string is orthogonal to the substrate.

公开(公告)号：US11481154B2

公开(公告)日：2022-10-25

申请号：US17149867

申请日：2021-01-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Deepanshu Dutta ,  James Kai ,  Johann Alsmeier ,  Jian Chen

IPC: G06F3/00 ,  G06F3/06 ,  G11C16/26 ,  G11C16/10 ,  H01L27/11582 ,  G11C16/04 ,  H01L27/11565

Abstract: An integrated memory assembly comprises a memory die and a control die bonded to the memory die. The memory die comprises a three dimensional non-volatile memory structure and a first plurality of sense amplifiers. The first plurality of sense amplifiers are connected to the memory structure and are positioned on a substrate of the memory die between the memory structure and the substrate such that the memory structure is directly above the first plurality of sense amplifiers. The control die comprises a second plurality of sense amplifiers that are connected to the memory structure. The first plurality of sense amplifiers and the second plurality of sense amplifiers are configured to be used to concurrently perform memory operations.

公开(公告)号：US09990987B2

公开(公告)日：2018-06-05

申请号：US15645182

申请日：2017-07-10

Applicant: Kabushiki Kaisha Toshiba ,  SanDisk Technologies LLC

Inventor： Tomoharu Tanaka ,  Jian Chen

IPC: G11C7/10 ,  G11C11/56 ,  G11C16/34 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/11521 ,  H01L27/115 ,  G11C16/12 ,  G11C16/04

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3459 ,  G11C16/3481 ,  G11C2211/5621 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.

公开(公告)号：US10707228B2

公开(公告)日：2020-07-07

申请号：US16284502

申请日：2019-02-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jixin Yu ,  Tae-Kyung Kim ,  Johann Alsmeier ,  Yan Li ,  Jian Chen

IPC: H01L27/088 ,  H01L27/11578 ,  G11C5/02 ,  G11C5/06

Abstract: Three-dimensional memory devices in the form of a memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Bit lines are electrically connected to an end portion of a respective one of the vertical semiconductor channels. Bump connection via structures contact a top surface of a respective one of the bit lines, in which each of the bump connection via structures has a greater lateral dimension along a lengthwise direction of the bit lines than along a widthwise direction of the bit lines. Metallic bump structures of another semiconductor die contact respective ones of the bump connection via structures to make respective electrical connections between the two dies.

公开(公告)号：US20200066745A1

公开(公告)日：2020-02-27

申请号：US16284502

申请日：2019-02-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jixin Yu ,  Tae-Kyung Kim ,  Johann Alsmeier ,  Yan Li ,  Jian Chen

IPC: H01L27/11578 ,  G11C5/06 ,  G11C5/02

Abstract: Three-dimensional memory devices in the form of a memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Bit lines are electrically connected to an end portion of a respective one of the vertical semiconductor channels. Bump connection via structures contact a top surface of a respective one of the bit lines, in which each of the bump connection via structures has a greater lateral dimension along a lengthwise direction of the bit lines than along a widthwise direction of the bit lines. Metallic bump structures of another semiconductor die contact respective ones of the bump connection via structures to make respective electrical connections between the two dies.

公开(公告)号：US10236058B2

公开(公告)日：2019-03-19

申请号：US15973644

申请日：2018-05-08

Applicant: Toshiba Memory Corporation ,  SanDisk Technologies LLC

Inventor： Tomoharu Tanaka ,  Jian Chen

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/12 ,  G11C16/34 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  G11C16/10

Abstract: A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.

公开(公告)号：US20180175054A1

公开(公告)日：2018-06-21

申请号：US15891574

申请日：2018-02-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish Baraskar ,  Raghuveer S. Makala ,  Ching-Huang Lu ,  Yao-Sheng Lee ,  Jian Chen

IPC: H01L27/11582 ,  H01L21/28 ,  H01L27/11565 ,  H01L23/532 ,  H01L21/02 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/768 ,  H01L23/528 ,  H01L23/53257 ,  H01L27/11565 ,  H01L29/40117 ,  H01L29/7926

Abstract: A three-dimensional non-volatile memory comprises a plurality of word line layers arranged alternatingly with a plurality of dielectric layers in a stack over a substrate. Higher word lines are implemented to be thicker than lower word lines in order to reduce variation in resistance among word lines.