公开(公告)号：US11387142B1

公开(公告)日：2022-07-12

申请号：US17208019

申请日：2021-03-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Koichi Matsuno ,  Masaaki Higashitani ,  Johann Alsmeier

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11529

Abstract: A semiconductor structure includes a semiconductor device, bit lines electrically connected to the semiconductor device, air gaps located between the bit lines, a capping-level material layer, a via-level dielectric material layer located between the bit lines and the capping-level material layer, and conductive via structures extending through the via-level dielectric material layer and contacting a top surface of a respective one of the bit lines. The capping-level material layer contains cavity-containing openings exposing the air gaps. The capping-level material layer contains protruding portions that extend into peripheral regions of the cavity-containing openings.

公开(公告)号：US11348649B2

公开(公告)日：2022-05-31

申请号：US16909826

申请日：2020-06-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kiyohiko Sakakibara ,  Hiroki Yabe ,  Ken Oowada ,  Masaaki Higashitani

IPC: G11C16/26 ,  G11C16/04 ,  G11C11/56 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/1157 ,  G11C16/24 ,  G11C16/34 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11519

Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.

公开(公告)号：US11276705B2

公开(公告)日：2022-03-15

申请号：US16552089

申请日：2019-08-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chen Wu ,  Peter Rabkin ,  Yangyin Chen ,  Masaaki Higashitani

IPC: H01L27/1158 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11514 ,  H01L27/11519 ,  H01L27/11553 ,  H01L27/11504 ,  H01L27/11507 ,  H01L27/11529

Abstract: A semiconductor structure includes a first semiconductor die containing a recesses, and a second semiconductor die which is embedded in the recess in the first semiconductor die and is bonded to the first semiconductor die.

公开(公告)号：US11094653B2

公开(公告)日：2021-08-17

申请号：US16682848

申请日：2019-11-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chen Wu ,  Peter Rabkin ,  Yangyin Chen ,  Masaaki Higashitani

IPC: H01L23/52 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

Abstract: A bonded assembly and a method of forming a bonded assembly includes providing a first semiconductor die including a first substrate, first semiconductor devices, and first bonding pads that are electrically connected to a respective node of the first semiconductor devices, providing a second semiconductor die including a second substrate, second semiconductor devices, and second bonding pads that are electrically connected to a respective node of the second semiconductor devices, forming a dielectric bonding pattern definition layer including bonding pattern definition openings therethrough over the second bonding pads, and bonding the second bonding pads to the first bonding pads, where the first metal pads expand through the bonding pattern definition openings and are bonded to a respective one of the second bonding pads.

公开(公告)号：US10957401B2

公开(公告)日：2021-03-23

申请号：US16909832

申请日：2020-06-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kiyohiko Sakakibara ,  Ippei Yasuda ,  Ken Oowada ,  Masaaki Higashitani

IPC: G11C16/26 ,  G11C11/56 ,  G11C16/08 ,  G11C16/24 ,  G11C16/34 ,  G11C16/04 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11519

Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.

公开(公告)号：US10755788B2

公开(公告)日：2020-08-25

申请号：US16233780

申请日：2018-12-27

Applicant: SanDisk Technologies LLC

Inventor： Peter Rabkin ,  Kwang-Ho Kim ,  Masaaki Higashitani ,  Yingda Dong

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/34 ,  H01L27/1157 ,  H01L27/11524

Abstract: An apparatus comprising an impedance compensation circuit is disclosed. The impedance compensation circuit compensates for impedance differences between a first pathway connected to a first transistor and a second pathway connected to a second transistor. However, rather than making a compensation based on a signal (e.g., voltage) applied to either the first or the second pathway, a compensation is made based on the signals (e.g., voltage pulses) applied to third and fourth pathways connected to the transistors.

公开(公告)号：US11996153B2

公开(公告)日：2024-05-28

申请号：US17556298

申请日：2021-12-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James Kai ,  Yuki Mizutani ,  Hisakazu Otoi ,  Masaaki Higashitani ,  Hiroyuki Ogawa

IPC: G11C16/08 ,  G11C8/14 ,  G11C16/04 ,  H01L23/48 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/0483 ,  G11C8/14 ,  H01L23/481 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of the contact regions and the memory array regions can reduce lateral offset of boundaries of the word line driver regions from boundaries of the contact regions.

公开(公告)号：US20240105265A1

公开(公告)日：2024-03-28

申请号：US17952846

申请日：2022-09-26

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Masaaki Higashitani ,  Abhijith Prakash ,  Dengtao Zhao

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/34

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/3445 ,  H01L25/0657

Abstract: A non-volatile memory system comprises a plurality of non-volatile memory cells divided into three or more tiers. The memory cells can be programmed, erased and read. In order to achieve uniform erase speed for the three or more tiers, the erase process comprises applying a larger voltage bias to control gates of non-volatile memory cells in the outer tiers than the voltage bias applied to control gates of non-volatile memory cells in one or more inner tiers.

公开(公告)号：US11901019B2

公开(公告)日：2024-02-13

申请号：US17666657

申请日：2022-02-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hua-Ling Cynthia Hsu ,  Masaaki Higashitani ,  YenLung Li ,  Chen Chen

IPC: G11C16/26 ,  G11C16/24 ,  H03M13/00 ,  H03M13/11 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/24 ,  H03M13/1111 ,  H03M13/611

Abstract: For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.

公开(公告)号：US11869877B2

公开(公告)日：2024-01-09

申请号：US17396291

申请日：2021-08-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lin Hou ,  Peter Rabkin ,  Yangyin Chen ,  Masaaki Higashitani

IPC: H01L23/32 ,  H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/32 ,  H01L23/481 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/2101 ,  H01L2224/32146 ,  H01L2224/73267 ,  H01L2224/83896 ,  H01L2225/06541 ,  H01L2924/37001

Abstract: A bonded assembly includes a first semiconductor die and a second semiconductor die that are bonded to each other by dielectric-to-dielectric bonding. First conductive via structures vertically extend through the second semiconductor die and a respective subset of the first dielectric material layers in the first semiconductor die, and contact a respective first metal interconnect structure in the first semiconductor die. Second conductive via structures vertically extend through a second substrate and a respective subset of the second dielectric material layers in the second semiconductor die, and contacting a respective second metal interconnect structure in the second semiconductor die. Redistribution metal interconnect structures located over a backside surface of the second substrate electrically connect the first conductive via structures and the second conductive via structures, and provide electrical interconnection between the first semiconductor die and the second semiconductor die.