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公开(公告)号：US20180277208A1
公开(公告)日：2018-09-27
申请号：US15714463
申请日：2017-09-25
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Deepak Kamalanathan , Juan P. Saenz , Tanmay Kumar , Emmanuelle Merced-Grafals , Sebastian J. M. Wicklein
CPC classification number: G11C13/0069 , G11C11/5664 , G11C11/5685 , G11C13/0007 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C2013/0073 , G11C2213/54 , G11C2213/71 , G11C2213/78 , G11C2213/79 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L45/08 , H01L45/1226 , H01L45/1246 , H01L45/146
Abstract: A memory device is provided that includes a memory controller coupled to a memory cell including a barrier modulated switching structure. The memory controller is adapted to program the memory cell to a first programming state, and program the memory cell to one of a plurality of target programming states from the first programming state.
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公开(公告)号：US10032908B1
公开(公告)日：2018-07-24
申请号：US15400244
申请日：2017-01-06
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Perumal Ratnam , Christopher Petti , Juan Saenz , Guangle Zhou , Abhijit Bandyopadhyay , Tanmay Kumar
IPC: H01L29/78 , H01L27/24 , H01L29/423 , H01L23/528 , H01L29/66
Abstract: A matrix rail structure is formed over a substrate. The matrix rail structure includes a pair of lengthwise sidewalls that extend along a first horizontal direction and comprises, or is at least partially subsequently replaced with, a set of at least one gate electrode rail extending along the first horizontal direction and straight-sidewalled gate dielectrics. A pair of vertical semiconductor channel strips and a pair of laterally-undulating gate dielectrics can be formed on sidewalls of the matrix rail structure for each vertical field effect transistor. At least one laterally-undulating gate electrode extending along the first horizontal direction is formed on the laterally-undulating gate dielectrics. Bottom active regions and top active regions are formed at end portions of the vertical semiconductor channel strips. The vertical field effect transistors can be formed as a two-dimensional array, and may be employed as access transistors for a three-dimensional memory device.
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公开(公告)号：US09923140B2
公开(公告)日：2018-03-20
申请号：US15269999
申请日：2016-09-20
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Ming-Che Wu , Tanmay Kumar
CPC classification number: H01L45/146 , G11C11/5685 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2213/71 , G11C2213/77 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/12 , H01L45/1226 , H01L45/1233 , H01L45/147 , H01L45/1608
Abstract: Systems and methods for providing a Barrier Modulated Cell (BMC) structure that may comprise a reversible resistance-switching memory element within a memory array are described. The BMC structure may include a barrier layer comprising a layer of amorphous germanium or amorphous silicon germanium paired with a conductive metal oxide, such as titanium dioxide (TiO2), strontium titanate (SrTiO3), or a binary metal oxide. The BMC structure may include a conductive metal oxide in series with an amorphous layer of a low bandgap material. The low bandgap material may comprise a semiconductor material with a bandgap energy (Eg) less than 1.0 eV. The improved BMC structure may be used for providing multi-level memory elements within a three dimensional memory array.
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Patent Agency Ranking
公开(公告)号：US20170309819A1
公开(公告)日：2017-10-26
申请号：US15269999
申请日：2016-09-20
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Ming-Che Wu , Tanmay Kumar
CPC classification number: H01L45/146 , G11C11/5685 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2213/71 , G11C2213/77 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/12 , H01L45/1226 , H01L45/1233 , H01L45/147 , H01L45/1608
Abstract: Systems and methods for providing a Barrier Modulated Cell (BMC) structure that may comprise a reversible resistance-switching memory element within a memory array are described. The BMC structure may include a barrier layer comprising a layer of amorphous germanium or amorphous silicon germanium paired with a conductive metal oxide, such as titanium dioxide (TiO2), strontium titanate (SrTiO3), or a binary metal oxide. The BMC structure may include a conductive metal oxide in series with an amorphous layer of a low bandgap material. The low bandgap material may comprise a semiconductor material with a bandgap energy (Eg) less than 1.0 eV. The improved BMC structure may be used for providing multi-level memory elements within a three dimensional memory array.
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公开(公告)号：US10283567B2
公开(公告)日：2019-05-07
申请号：US15441284
申请日：2017-02-24
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Juan Saenz , Deepak Kamalanathan , Guangle Zhou , Ming-Che Wu , Tanmay Kumar
Abstract: A method is provided that includes forming a word line above a substrate, the word line disposed in a first direction, forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material between the word line and the bit line, the nonvolatile memory material including a semiconductor material layer and conductive oxide material layer, forming a first barrier material layer between the word line and the nonvolatile memory material, forming a second barrier material layer between the bit line and the nonvolatile memory material, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line.
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公开(公告)号：US10276792B2
公开(公告)日：2019-04-30
申请号：US15890296
申请日：2018-02-06
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Ming-Che Wu , Tanmay Kumar
Abstract: Systems and methods for providing a Barrier Modulated Cell (BMC) structure that may comprise a reversible resistance-switching memory element within a memory array are described. The BMC structure may include a barrier layer comprising a layer of amorphous germanium or amorphous silicon germanium paired with a conductive metal oxide, such as titanium dioxide (TiO2), strontium titanate (SrTiO3), or a binary metal oxide. The BMC structure may include a conductive metal oxide in series with an amorphous layer of a low bandgap material. The low bandgap material may comprise a semiconductor material with a bandgap energy (Eg) less than 1.0 eV. The improved BMC structure may be used for providing multi-level memory elements within a three dimensional memory array.
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公开(公告)号：US20180159033A1
公开(公告)日：2018-06-07
申请号：US15890296
申请日：2018-02-06
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Ming-Che Wu , Tanmay Kumar
CPC classification number: H01L45/146 , G11C11/5685 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2213/71 , G11C2213/77 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/12 , H01L45/1226 , H01L45/1233 , H01L45/147 , H01L45/1608
Abstract: Systems and methods for providing a Barrier Modulated Cell (BMC) structure that may comprise a reversible resistance-switching memory element within a memory array are described. The BMC structure may include a barrier layer comprising a layer of amorphous germanium or amorphous silicon germanium paired with a conductive metal oxide, such as titanium dioxide (TiO2), strontium titanate (SrTiO3), or a binary metal oxide. The BMC structure may include a conductive metal oxide in series with an amorphous layer of a low bandgap material. The low bandgap material may comprise a semiconductor material with a bandgap energy (Eg) less than 1.0 eV. The improved BMC structure may be used for providing multi-level memory elements within a three dimensional memory array.
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公开(公告)号：US09806256B1
公开(公告)日：2017-10-31
申请号：US15299919
申请日：2016-10-21
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Ming-Che Wu , Chuanbin Pan , Guangle Zhou , Tanmay Kumar
CPC classification number: H01L45/124 , G11C13/0007 , G11C13/0026 , G11C13/0028 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2213/51 , G11C2213/52 , H01L27/2436 , H01L45/08 , H01L45/085 , H01L45/1246 , H01L45/1266 , H01L45/146 , H01L45/1675
Abstract: A resistive memory device includes a first electrode, a sidewall spacer electrode located on a sidewall of a dielectric material contacting the first electrode, a resistive memory cell containing a resistive memory material and contacting the sidewall spacer electrode, and a second electrode containing the resistive memory cell.
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