公开(公告)号：US20150263166A1

公开(公告)日：2015-09-17

申请号：US14725064

申请日：2015-05-29

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Zia HOSSAIN ,  Gordon M. GRIVNA

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/7827 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7813

Abstract: An electronic device can include a transistor structure, including a patterned semiconductor layer overlying a substrate and having a primary surface. The electronic device can further include first conductive structures within each of a first trench and a second trench, a gate electrode within the first trench and electrically insulated from the first conductive structure, a first insulating member disposed between the gate electrode and the first conductive structure within the first trench, and a second conductive structure within the second trench. The second conductive structure can be electrically connected to the first conductive structures and is electrically insulated from the gate electrode. The electronic device can further include a second insulating member disposed between the second conductive structure and the first conductive structure within the second trench. Processing sequences can be used that simplify formation of the features within the electronic device.

Abstract translation: 电子器件可以包括晶体管结构，其包括覆盖在衬底上并具有主表面的图案化半导体层。 电子器件还可以包括在第一沟槽和第二沟槽的每一个内的第一导电结构，第一沟槽内的栅电极和与第一导电结构电绝缘的第一绝缘构件，设置在栅电极和第一导电结构之间 在第一沟槽内，以及在第二沟槽内的第二导电结构。 第二导电结构可以电连接到第一导电结构并且与栅电极电绝缘。 电子设备还可以包括设置在第二导电结构和第二沟槽内的第一导电结构之间的第二绝缘构件。 可以使用简化电子设备内的特征的形成的处理顺序。

公开(公告)号：US20150108569A1

公开(公告)日：2015-04-23

申请号：US14297204

申请日：2014-06-05

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gordon M. GRIVNA ,  Zia HOSSAIN ,  Ali SALIH

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/76205 ,  H01L21/76816 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

Abstract: In an embodiment, a method of forming a semiconductor may include forming a plurality of active trenches and forming a termination trench substantially surrounding an outer periphery of the plurality of active trenches. The method may also include forming at least one active trench of the plurality of active trenches having corners linking trench ends to sides of active trenches wherein each active trench of the plurality of active trenches has a first profile along the first length and a second profile at or near the trench ends; and forming a termination trench substantially surrounding an outer periphery of the plurality of active trenches and having a second profile wherein one of the first profile or the second profile includes a non-linear shape.

Abstract translation: 在一个实施例中，形成半导体的方法可以包括形成多个有源沟槽并且形成基本上围绕多个有源沟槽的外周边的端接沟槽。 该方法还可以包括形成多个有源沟槽中的至少一个有源沟槽，其具有将沟槽端部连接到有源沟槽侧面的拐角，其中多个有源沟槽中的每个有源沟槽具有沿第一长度的第一分布， 或在沟槽末端附近; 以及形成基本上围绕所述多个有源沟槽的外周边的终端沟槽，并且具有第二形状，其中所述第一形状或所述第二形状中的一个包括非线性形状。

公开(公告)号：US20240030293A1

公开(公告)日：2024-01-25

申请号：US18479630

申请日：2023-10-02

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gordon M. GRIVNA

IPC: H01L29/165 ,  H01L21/285 ,  H01L29/06

CPC classification number: H01L29/165 ,  H01L21/28562 ,  H01L29/0688 ,  H01L28/60 ,  H01L28/55 ,  H01L28/40

Abstract: A method of manufacturing an electronic device includes providing a work piece comprising a first material, a first side, a second side opposite to the first side, and a first CTE. The method includes providing recesses extending into the work piece from the first side and comprising a pattern. The method includes providing a second material comprising a second CTE within the recesses and over the first material between the recesses. The method includes providing a third material comprising a third CTE over one of the second side or the second material. The third CTE and the second CTE are different than the first CTE.

公开(公告)号：US20220271118A1

公开(公告)日：2022-08-25

申请号：US17249279

申请日：2021-02-25

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Rick Carlton JEROME ,  Gordon M. GRIVNA ,  Kevin Alexander STEWART ,  David T. PRICE ,  Jeffrey Peter GAMBINO

IPC: H01L49/02 ,  H01C7/00

Abstract: An integrated circuit die includes a silicon chromium (SiCr) thin film resistor disposed on a first oxide layer. The SiCr thin film resistor has a resistor body and a resistor head. A second oxide layer overlays the SiCr thin film resistor. The second oxide layer has an opening exposing a surface of the resistor head. A metal pad is disposed in the opening in the second oxide layer and is contact with the surface of the resistor head exposed by the opening. Further, an interlevel dielectric layer is disposed on the second oxide layer overlaying the SiCr thin film resistor. A metal-filled via extends from a top surface of interlevel dielectric layer through the interlevel dielectric layer and contacts the metal pad disposed in the opening in the second oxide layer.

公开(公告)号：US20210305096A1

公开(公告)日：2021-09-30

申请号：US17304136

申请日：2021-06-15

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： George CHANG ,  Yusheng LIN ,  Gordon M. GRIVNA ,  Takashi NOMA

IPC: H01L21/78 ,  H01L21/683 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

Abstract: In a general aspect, a fan-out wafer level package (FOWLP) can include a semiconductor die having an active surface, a backside surface, a plurality of side surfaces, each side surface of the plurality of side surfaces extending between the active surface and the backside surface, a plurality of conductive bumps disposed on the active surface, and an insulating layer disposed on a first portion of the active surface between the conductive bumps. The FOWLP can also include a molding compound encapsulating the backside surface, the plurality of side surfaces, and a second portion of the active surface between the conductive bumps and a perimeter edge of the active surface. The FOWLP can also include a signal distribution structure disposed on the conductive bumps, the insulating layer and the molding compound. The signal distribution structure can be configured to provide respective electrical connections to the plurality of conductive bumps.

公开(公告)号：US20210296176A1

公开(公告)日：2021-09-23

申请号：US17248514

申请日：2021-01-28

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Srinivasa Reddy YEDURU ,  George CHANG ,  Gordon M. GRIVNA

IPC: H01L21/78 ,  H01L21/268 ,  H01L21/3065

Abstract: A method for singulating a semiconductor wafer includes providing the semiconductor wafer having a plurality of semiconductor devices adjacent to a first surface, the plurality of semiconductor devices separated by spaces corresponding to where singulation lines will be formed. The method includes providing an alignment structure adjacent to the first surface and providing a material on a second surface of the semiconductor wafer, wherein the material is absent on the second surface directly below the alignment structure. The method includes passing an IR signal through the semiconductor wafer from the second surface to the first surface where the material is absent to detect the alignment structure and align a singulation device to the spaces where the singulation lines on will be formed. The method includes using the singulation device to remove portions of the layer of material aligned to the singulation lines and thereafter plasma etching the semiconductor wafer from the first surface to the second surface through the spaces to form the singulation lines thereby singulating the semiconductor wafer.

公开(公告)号：US20200350424A1

公开(公告)日：2020-11-05

申请号：US16947085

申请日：2020-07-17

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Meng-Chia LEE ,  Ralph N. WALL ,  Mingjiao LIU ,  Shamsul Arefin KHAN ,  Gordon M. GRIVNA

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/08

Abstract: In a general aspect, method of producing an insulated-gate bipolar transistor (IGBT) device can include forming a termination structure in an inactive region. The inactive region at least partial surround an active region. The method can also include forming a trench extending along a longitudinal axis in the active region. A first mesa can define a first sidewall of the trench, and a second mesa can define a second sidewall of the trench. The first mesa and the second mesa can be parallel with the trench. The method can further include forming, in at least a portion of the first mesa, an active segment of the IGBT device, and, forming, in at least a portion of the second mesa, an inactive segment of the IGBT device.

公开(公告)号：US20190295895A1

公开(公告)日：2019-09-26

申请号：US16438870

申请日：2019-06-12

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gordon M. GRIVNA

IPC: H01L21/78 ,  H01L21/304 ,  H01L21/683 ,  H01L21/67 ,  H01L23/544

Abstract: A method of singulating a wafer includes providing a wafer having a plurality of die formed as part of the wafer and separated from each other by spaces. The wafer has first and second opposing major surfaces, a layer of material atop the second major surface, and portions of the layer of material are adapted to remain atop surfaces of the plurality of die after completion of the method of singulating the wafer. The method includes placing the wafer onto a carrier substrate and singulating the wafer through the spaces to form singulation lines, wherein singulating comprises leaving at least a portion of the layer of material under the singulation lines. The method includes separating the layer of material under the singulation lines by applying pressure to the wafer and applying high frequency vibrations to fatigue the layer of material.

公开(公告)号：US20190043828A1

公开(公告)日：2019-02-07

申请号：US16149360

申请日：2018-10-02

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gordon M. GRIVNA

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L21/78

Abstract: A semiconductor substrate contains a plurality of semiconductor die with a saw street between the semiconductor die. A plurality of bumps is formed over a first surface of the semiconductor die. An insulating layer is formed over the first surface of the semiconductor die between the bumps. A portion of a second surface of the semiconductor die is removed and a conductive layer is formed over the remaining second surface. The semiconductor substrate is disposed on a dicing tape, the semiconductor substrate is singulated through the saw street while maintaining position of the semiconductor die, and the dicing tape is expanded to impart movement of the semiconductor die and increase a space between the semiconductor die. An encapsulant is deposited over the semiconductor die and into the space between the semiconductor die. A channel is formed through the encapsulant between the semiconductor die to separate the semiconductor die.

公开(公告)号：US20180356296A1

公开(公告)日：2018-12-13

申请号：US15621093

申请日：2017-06-13

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jaume ROIG-GUITART ,  Herbert DE VLEESCHOUWER ,  Gordon M. GRIVNA

IPC: G01K7/20 ,  G01K7/01 ,  H01L29/08

Abstract: An electronic device can include a temperature sensor. The temperature sensor can include a drain electrode including drain fingers spaced apart from the source fingers; a source electrode including source fingers spaced apart from the drain fingers; and a gate electrode including a runner, gate fingers and a conductive bridge. In an embodiment, the runner includes a first portion and a second portion spaced apart from the first portion, the gate fingers are coupled to the runner and each gate finger is disposed between a pair of the source and drain fingers. The conductive bridge connects at least two gate fingers, wherein the conductive bridge is along a conduction path between the first and second portions of the runner. Designs for the temperature sensor may provide a more accurate temperature measurement reflective of a transistor within the electronic device.