公开(公告)号：US20160343870A1

公开(公告)日：2016-11-24

申请号：US15230732

申请日：2016-08-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshitaka YAMAMOTO ,  Tetsuhiro TANAKA ,  Takayuki INOUE ,  Hideomi SUZAWA

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/792 ,  H01L21/441 ,  H01L29/51 ,  H01L29/49 ,  H01L21/465 ,  H01L21/02 ,  H01L29/24 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L21/0214 ,  H01L21/02181 ,  H01L21/02266 ,  H01L21/02274 ,  H01L21/28194 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31645 ,  H01L21/32136 ,  H01L21/441 ,  H01L21/465 ,  H01L21/473 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/40117 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78693 ,  H01L29/78696 ,  H01L29/792

Abstract: A semiconductor device in which the threshold is adjusted is provided. In a transistor including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and an electron trap layer between the gate electrode and the semiconductor, the electron trap layer includes crystallized hafnium oxide. The crystallized hafnium oxide is deposited by a sputtering method using hafnium oxide as a target. When the substrate temperature is Tsub (° C.) and the proportion of oxygen in an atmosphere is P (%) in the sputtering method, P≧45−0.15×Tsub is satisfied. The crystallized hafnium oxide has excellent electron trapping properties. By the trap of an appropriate number of electrons, the threshold of the semiconductor device can be adjusted.

公开(公告)号：US20150069393A1

公开(公告)日：2015-03-12

申请号：US14547285

申请日：2014-11-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masashi TSUBUKU ,  Takayuki INOUE ,  Suzunosuke HIRAISHI ,  Erumu KIKUCHI ,  Hiromichi GODO ,  Shuhei YOSHITOMI ,  Koki INOUE ,  Akiharu MIYANAGA ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  H01L29/40

CPC classification number: H01L29/7869 ,  H01L29/408

Abstract: Manufactured is a transistor including an oxide semiconductor layer, a source electrode layer and a drain electrode layer overlapping with part of the oxide semiconductor layer, a gate insulating layer overlapping with the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode overlapping with part of the oxide semiconductor layer with the gate insulating layer provided therebetween, wherein, after the oxide semiconductor layer which is to be a channel formation region is irradiated with light and the light irradiation is stopped, a relaxation time of carriers in photoresponse characteristics of the oxide semiconductor layer has at least two kinds of modes: τ1 and τ2, τ1

Abstract translation: 制造的是包括与氧化物半导体层的一部分重叠的氧化物半导体层，源极电极层和漏极电极层，与氧化物半导体层重叠的栅极绝缘层，源极电极层和漏极电极层的晶体管， 以及与所述氧化物半导体层的与氧化物半导体层的一部分重叠的栅电极，其间设置有栅极绝缘层，其中，在作为沟道形成区域的氧化物半导体层被照射光并停止光照射之后，弛豫时间 氧化物半导体层的光响应特性中的载流子具有至少两种模式：τ1和τ2，τ1<τ2，τ2为300秒以下。 此外，制造包括晶体管的半导体器件。

公开(公告)号：US20130270679A1

公开(公告)日：2013-10-17

申请号：US13908047

申请日：2013-06-03

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tomokazu YOKOI ,  Takayuki INOUE ,  Makoto FURUNO

IPC: H01L29/12

CPC classification number: H01L29/12 ,  H01M4/0428 ,  H01M4/134 ,  H01M4/366 ,  H01M4/386

Abstract: Provided are a semiconductor film including silicon microstructures formed at high density, and a manufacturing method thereof. Further, provided are a semiconductor film including silicon microstructures whose density is controlled, and a manufacturing method thereof. Furthermore, a power storage device with improved charge-discharge capacity is provided. A manufacturing method in which a semiconductor film with a silicon layer including silicon structures is formed over a substrate with a metal surface is used. The thickness of a silicide layer formed by reaction between the metal and the silicon is controlled, so that the grain sizes of silicide grains formed at an interface between the silicide layer and the silicon layer are controlled and the shapes of the silicon structures are controlled. Such a semiconductor film can be applied to an electrode of a power storage device.

Abstract translation: 提供了包括以高密度形成的硅微结构的半导体膜及其制造方法。 此外，提供了包括其密度被控制的硅微结构的半导体膜及其制造方法。 此外，提供了具有改善的充放电容量的蓄电装置。 使用其中在具有金属表面的基板上形成具有包括硅结构的硅层的半导体膜的制造方法。 控制由金属与硅之间的反应形成的硅化物层的厚度，从而控制在硅化物层和硅层之间的界面处形成的硅化物晶粒的晶粒尺寸，并且控制硅结构的形状。 这样的半导体膜可以应用于蓄电装置的电极。

公开(公告)号：US20150325704A1

公开(公告)日：2015-11-12

申请号：US14803483

申请日：2015-07-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Yusuke NONAKA ,  Takayuki INOUE ,  Masashi TSUBUKU ,  Kengo AKIMOTO ,  Akiharu MIYANAGA

IPC: H01L29/786 ,  H01L29/04

CPC classification number: H01L29/78606 ,  H01L23/552 ,  H01L23/564 ,  H01L29/04 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An object is to manufacture a semiconductor device including an oxide semiconductor film, which has stable electric characteristics and high reliability. A crystalline oxide semiconductor film is formed, without performing a plurality of steps, as follows: by utilizing a difference in atomic weight of plural kinds of atoms included in an oxide semiconductor target, zinc with low atomic weight is preferentially deposited on an oxide insulating film to form a seed crystal including zinc; and tin, indium, or the like with high atomic weight is deposited on the seed crystal while causing crystal growth. Further, a crystalline oxide semiconductor film is formed by causing crystal growth using a seed crystal with a hexagonal crystal structure including zinc as a nucleus, whereby a single crystal oxide semiconductor film or a substantially single crystal oxide semiconductor film is formed.

Abstract translation: 本发明的目的是制造具有稳定的电特性和高可靠性的氧化物半导体膜的半导体装置。 通过利用包含在氧化物半导体靶中的多种原子的原子量的差异，形成结晶氧化物半导体膜，而不进行多个步骤，优选将低原子量的锌沉积在氧化物绝缘膜上 形成包含锌的晶种; 并且具有高原子量的锡，铟等沉积在晶种上同时引起晶体生长。 此外，通过使用具有包含锌作为核的六方晶系结构的晶种进行晶体生长来形成结晶氧化物半导体膜，从而形成单晶氧化物半导体膜或大致单晶氧化物半导体膜。

公开(公告)号：US20150024577A1

公开(公告)日：2015-01-22

申请号：US14330481

申请日：2014-07-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi KATO ,  Yasuhiko TAKEMURA ,  Tetsuhiro TANAKA ,  Takayuki INOUE ,  Toshihiko TAKEUCHI ,  Yasumasa YAMANE ,  Shunpei YAMAZAKI

IPC: G11C16/04 ,  H01L27/115 ,  G11C16/20

CPC classification number: G11C16/0466 ,  G11C16/20 ,  H01L21/28282 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/11568

Abstract: A manufacturing method of a semiconductor device in which the threshold is corrected is provided. In a semiconductor device including a plurality of transistors each includes a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and a charge trap layer between the gate electrode and the semiconductor, electrons are trapped in the charge trap layer by performing heat treatment and, simultaneously, keeping a potential of the gate electrode higher than that of the source or drain electrode for 1 second or more. By this process, the threshold increases and Icut decreases. A circuit for supplying a signal to the gate electrode and a circuit for supplying a signal to the source or drain electrode are electrically separated from each other. The process is performed in the state where the potential of the former circuit is set higher than the potential of the latter circuit.

Abstract translation: 提供了其中校正阈值的半导体器件的制造方法。 在包括多个晶体管的半导体器件中，每个包括半导体，与半导体电连接的源电极或漏电极，栅电极和栅电极与半导体之间的电荷陷阱层，电子被俘获在电荷陷阱层 通过进行热处理，同时保持栅电极的电位高于源电极或漏电极的电位1秒以上。 通过该过程，阈值增加并且Icut减小。 用于向栅电极提供信号的电路和用于向源电极或漏电极提供信号的电路彼此电分离。 该处理在前一电路的电位被设置为高于后一电路的电位的状态下执行。

公开(公告)号：US20150008428A1

公开(公告)日：2015-01-08

申请号：US14313154

申请日：2014-06-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshitaka YAMAMOTO ,  Tetsuhiro TANAKA ,  Toshihiko TAKEUCHI ,  Yasumasa YAMANE ,  Takayuki INOUE ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L27/1156 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78696 ,  H01L2029/42388

Abstract: A manufacturing method of a semiconductor device in which the threshold is adjusted to an appropriate value is provided. The semiconductor device includes a semiconductor, a source or drain electrode electrically connected to the semiconductor, a first gate electrode and a second gate electrode between which the semiconductor is sandwiched, an electron trap layer between the first gate electrode and the semiconductor, and a gate insulating layer between the second gate electrode and the semiconductor. By keeping a potential of the first gate electrode higher than a potential of the source or drain electrode for 1 second or more while heating, electrons are trapped in the electron trap layer. Consequently, threshold is increased and Icut is reduced.

Abstract translation: 提供了将阈值调整为适当值的半导体器件的制造方法。 半导体器件包括半导体，与半导体电连接的源极或漏极，第一栅电极和第二栅电极，半导体夹在其间，第一栅电极和半导体之间的电子陷阱层和栅极 第二栅电极和半导体之间的绝缘层。 通过在加热的同时保持第一栅电极的电位高于源极或漏极的电位1秒以上，电子被捕获在电子阱层中。 因此，阈值增加并且Icut减小。