公开(公告)号：US11450366B2

公开(公告)日：2022-09-20

申请号：US17331918

申请日：2021-05-27

Applicant: SK hynix Inc.

Inventor： Jin Ha Hwang ,  Kwang Soon Kim ,  Dae Ho Yang ,  Yo Han Jeong ,  Jun Sun Hwang

IPC: G11C7/22 ,  G11C7/10

Abstract: A dividing circuit system includes a first dividing circuit and a second dividing circuit. The first dividing circuit performs a reset operation based on a reset control signal and generates second and fourth divided clock signals. The second dividing circuit performs a reset operation based on the reset control signal and generates first and third divided clock signals.

公开(公告)号：US10164634B2

公开(公告)日：2018-12-25

申请号：US15920149

申请日：2018-03-13

Applicant: SK hynix Inc.

Inventor： Yo Han Jeong

IPC: H03K19/00 ,  H03K19/003 ,  H03K17/687

Abstract: An impedance calibration circuit includes a first detection unit configured to generate a first pull-up impedance detection signal according to a resistance value of an internal reference resistor, a second detection unit configured to generate a second pull-up impedance detection signal according to a resistance value of an external reference resistor coupled to an external reference resistor pad, a switching unit configured to select the first pull-up impedance detection signal or the second pull-up impedance detection signal according to the internal impedance calibration enable signal and output the selected pull-up impedance detection signal, and an impedance calibration signal generation unit configured to generate a plurality of impedance calibration signals according to an output of the switching unit.

公开(公告)号：US09859910B1

公开(公告)日：2018-01-02

申请号：US15632648

申请日：2017-06-26

Applicant: SK hynix Inc.

Inventor： Dong Hyun Kim ,  Soon Ku Kang ,  Kwan Su Shon ,  Yo Han Jeong ,  Eun Ji Choi

IPC: H03M1/34 ,  H03M1/12 ,  H04N5/374 ,  H04N5/378 ,  H03M1/06 ,  H03K5/24 ,  H03M1/56 ,  H03M1/10 ,  H03M1/80 ,  H03M1/00

CPC classification number: H03M1/1295 ,  H03K5/2481 ,  H03K5/249 ,  H03M1/00 ,  H03M1/0607 ,  H03M1/0678 ,  H03M1/1019 ,  H03M1/12 ,  H03M1/462 ,  H03M1/56 ,  H03M1/804 ,  H04N5/3742 ,  H04N5/378

Abstract: An analog to digital converter includes a first DAC unit configured to vary a level of a reference voltage output through a first node according to a first code, a second DAC unit coupled in parallel to the first DAC unit on the basis of the first node and configured to vary the level of the reference voltage according to a second code, a comparator configured to generate a comparison result signal by comparing an input voltage and the reference voltage, and at least one register array configured to store the first code and the second code with initial values and store the first code and the second code by varying values of the first code and the second code according to the comparison result signal.

公开(公告)号：US11799481B2

公开(公告)日：2023-10-24

申请号：US17549316

申请日：2021-12-13

Applicant: SK hynix Inc.

Inventor： Jin Ha Hwang ,  Yo Han Jeong ,  Eun Ji Choi

IPC: H03K19/0185 ,  H03K19/20 ,  G11C7/10 ,  H03K19/08

CPC classification number: H03K19/018521 ,  G11C7/1084 ,  G11C7/1096 ,  H03K19/08 ,  H03K19/20

Abstract: The present technology may include: a first logic gate coupled to an internal voltage terminal and configured to receive data and invert and output the data according to a first enable signal; and a second logic gate coupled to the internal voltage terminal and configured to invert an output of the first logic gate and to output an inverted output as a first buffer signal according to the first enable signal, and configured to compensate for a duty skew of the first buffer signal according to a level of an external voltage.

公开(公告)号：US11671076B2

公开(公告)日：2023-06-06

申请号：US17979583

申请日：2022-11-02

Applicant: SK hynix Inc.

Inventor： Dae Ho Yang ,  Kwan Su Shon ,  Yo Han Jeong ,  Dong Shin Jo

IPC: H03K3/017 ,  G11C7/22

CPC classification number: H03K3/017 ,  G11C7/222

Abstract: Devices and methods for detecting and correcting duty cycles are described. An input switching unit is configured to perform at least one of an operation of outputting differential input signals as a first combination of first and second output signals and an operation of outputting the differential input signals as a second combination of the first and second output signals, according to one of a plurality of control signals. A comparator is configured to receive the first output signal through a first input terminal thereof, to receive the second output signal through a second input terminal thereof, to generate duty detection signals by comparing the signal of the first input terminal and the signal of the second input terminal according to at least another one of the plurality of control signals, and to adjust an offset of at least one of the first input terminal and the second input terminal.

公开(公告)号：US11190185B2

公开(公告)日：2021-11-30

申请号：US16900537

申请日：2020-06-12

Applicant: SK hynix Inc.

Inventor： Eun Ji Choi ,  Jin Ha Hwang ,  Keun Seon Ahn ,  Yo Han Jeong

IPC: H03K19/00 ,  H03K19/0185

Abstract: An impedance calibration circuit may include: a first driver having an impedance calibrated according to a first impedance control code, and configured to drive an output terminal according to first data; a second driver having an impedance calibrated according to a second impedance control code, and configured to drive the output terminal according to second data; and an impedance calibration circuit configured to calibrate the first impedance control code to a first target value set to a resistance value of an external resistor, and calibrate the second impedance control code to a second target value different from the resistance value of the external resistor.

公开(公告)号：US10964364B2

公开(公告)日：2021-03-30

申请号：US16806822

申请日：2020-03-02

Applicant: SK hynix Inc.

Inventor： Kwan Su Shon ,  Yo Han Jeong

IPC: G11C7/22 ,  G11C7/10 ,  G11C5/02

Abstract: A semiconductor device includes a plurality of stacked dies electrically connected with each other. Each of the stacked dies includes a data path, a strobe path, a stack information generation circuit, and a delay control circuit. The data path transmits a data signal. The strobe path transmits a data strobe signal. The stack information generation circuit generates stack information representing a number of the dies. The delay control circuit controls a delay time of at least one of the data path and the strobe path based on the stack information.

公开(公告)号：US10679684B2

公开(公告)日：2020-06-09

申请号：US16253827

申请日：2019-01-22

Applicant: SK hynix Inc.

Inventor： Keun Seon Ahn ,  Yo Han Jeong ,  Jin Ha Hwang

IPC: G11C8/08 ,  G11C11/408 ,  G11C7/10 ,  G11C8/06 ,  G11C29/02

Abstract: The present disclosure relates to a data out buffer and a memory device having the same. The data out buffer includes a pull-up main driver, coupled between a power supply terminal and an output terminal, configured to output data of a high level; and a pull-down main driver, coupled between the output terminal and a ground terminal, configured to output data of a low level, wherein the pull-up main driver comprises a main pull-up transistor of a first type; and a plurality of first trim transistors, each of a second type.

公开(公告)号：US10091032B2

公开(公告)日：2018-10-02

申请号：US15657412

申请日：2017-07-24

Applicant: SK hynix Inc.

Inventor： Kwan Su Shon ,  Yo Han Jeong

IPC: H03H7/30 ,  H04L25/03 ,  H04L25/06

Abstract: An equalization circuit may include a buffer configured to sense an input signal according to a reference voltage. The equalization circuit may include a reference voltage generator configured to generate the reference voltage. The reference voltage may be changed in conformity with noise of the input signal.

公开(公告)号：US11837310B2

公开(公告)日：2023-12-05

申请号：US17569144

申请日：2022-01-05

Applicant: SK hynix Inc.

Inventor： Jaehyeong Hong ,  In Seok Kong ,  Gwan Woo Kim ,  Jae Young Park ,  Kwan Su Shon ,  Soon Sung An ,  Daeho Yang ,  Sung Hwa Ok ,  Junseo Jang ,  Yo Han Jeong ,  Eun Ji Choi

IPC: G11C29/44 ,  G11C29/12 ,  H03K5/15 ,  H03K19/17736 ,  H03K5/156 ,  H03K19/20

CPC classification number: G11C29/4401 ,  G11C29/12015 ,  H03K5/1565 ,  H03K5/15066 ,  H03K19/1774 ,  H03K19/20

Abstract: The present disclosure relates to a memory device for correcting a pulse duty ratio and a memory system including the same, and relates to a memory device which corrects the duty ratio of a primary pulse of a memory device control signal, and a memory system including the same.