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    Phase mixing circuit, and semiconductor apparatus and semiconductor system including the same
    12.
    发明授权
    Phase mixing circuit, and semiconductor apparatus and semiconductor system including the same 有权
    相位混合电路，以及包括其的半导体装置及半导体系统

    公开(公告)号：US09197202B2

    公开(公告)日：2015-11-24

    申请号：US14092251

    申请日：2013-11-27

    Applicant: SK hynix Inc.

    Inventor： Jae Min Jang ,  Yong Ju Kim ,  Dae Han Kwon ,  Kil Ho Cha

    IPC: H03H11/16 ,  H03K3/00 ,  H03K5/13

    CPC classification number: H03K5/131

    Abstract: A phase mixing circuit includes a first mixing unit configured to mix phases of first and second clocks at a predetermined ratio, and generate a first mixed signal; a second mixing unit configured to mix phases of an inverted signal of the first clock and an inverted signal of the second clock at the predetermined ratio, and generate a second mixed signal; and an output unit configured to generate an output signal based on of the first and second mixed signals.

    Abstract translation: 相位混合电路包括：第一混合单元，被配置为以预定比率混合第一和第二时钟的相位，并产生第一混合信号; 第二混合单元，被配置为以预定比率混合第一时钟的反相信号的相位和第二时钟的反相信号，并产生第二混合信号; 以及输出单元，被配置为基于第一和第二混合信号产生输出信号。

    Test circuit for testing refresh circuitry of a semiconductor memory device
    13.
    发明授权
    Test circuit for testing refresh circuitry of a semiconductor memory device 有权
    用于测试半导体存储器件的刷新电路的测试电路

    公开(公告)号：US09076550B2

    公开(公告)日：2015-07-07

    申请号：US13720319

    申请日：2012-12-19

    Applicant: SK hynix Inc.

    Inventor： Jong Ho Son ,  Yong Ju Kim

    IPC: G11C11/40 ,  G01K7/42 ,  G11C11/406 ,  G11C29/50 ,  G11C29/56 ,  G11C11/41

    CPC classification number: G11C11/40626 ,  G01K7/425 ,  G11C11/41 ,  G11C29/50016 ,  G11C29/56 ,  G11C29/56012 ,  G11C2029/5002

    Abstract: A test circuit of a semiconductor apparatus includes a test temperature information generation section, an erroneous operation prevention unit, and a refresh cycle adjustment unit. The test temperature information generation section outputs test temperature information having a plurality of bits in a test operation mode, and irregularly changes logic values of the plurality of bits and transition time points of the logic values. The erroneous operation prevention unit generates a temperature compensation signal in response to the test temperature information. The refresh cycle adjustment unit changes a cycle of a reference refresh signal in response to the temperature compensation signal, and generates a refresh signal.

    Abstract translation: 半导体装置的测试电路包括测试温度信息产生部分，错误操作防止单元和刷新周期调节单元。 测试温度信息生成部分在测试操作模式下输出具有多个位的测试温度信息，并且不规则地改变逻辑值的多个位的逻辑值和转换时间点。 错误操作防止单元根据测试温度信息生成温度补偿信号。 刷新周期调整单元响应于温度补偿信号改变参考刷新信号的周期，并产生刷新信号。

    Memory apparatus and method of wear-leveling of a memory apparatus
    16.
    发明授权
    Memory apparatus and method of wear-leveling of a memory apparatus 有权

    公开(公告)号：US10310972B1

    公开(公告)日：2019-06-04

    申请号：US16271431

    申请日：2019-02-08

    Applicant: SK hynix Inc.

    Inventor： Donggun Kim ,  Yong Ju Kim ,  Do Sun Hong

    IPC: G11C16/04 ,  G06F12/02

    Abstract: A memory apparatus and a method of wear-leveling of a memory apparatus may be provided. The memory apparatus may include a memory having a plurality of storage blocks and a plurality of free blocks. The memory apparatus may include a memory controller configured for performing a first global wear-leveling to move data of a first storage block, which is a hot block among the storage blocks, to a first free block among the free blocks. The memory apparatus may include a memory controller configured for remapping a result of a logic operation of a logical page address of each of the pages in the first storage block and a first security refresh key to a physical page address of each of the pages in the first free block.

    Delay circuit and semiconductor apparatus including the same
    19.
    发明授权
    Delay circuit and semiconductor apparatus including the same 有权
    延迟电路和包括其的半导体装置

    公开(公告)号：US08823431B2

    公开(公告)日：2014-09-02

    申请号：US13712625

    申请日：2012-12-12

    Applicant: SK hynix Inc.

    Inventor： Jae Min Jang ,  Yong Ju Kim ,  Dae Han Kwon ,  Hae Rang Choi

    IPC: H03L7/06

    CPC classification number: H03L7/08 ,  H03L7/0805 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/093

    Abstract: A delay circuit includes a clock delay line, a command delay line, a delay line control block, and a shared shift register block. The clock delay line delays an input clock and generates a delayed clock. The command delay line delays a command signal and generates a delayed command signal. The delay line control block generates a control signal according to a result of comparing phases of a feedback clock which is generated as the delayed clock is delayed by a modeled delay value and the input clock. The shared shift register block sets delay amounts of the clock delay line and the command delay line to be substantially the same with each other, in response to the control signal.

    Abstract translation: 延迟电路包括时钟延迟线，命令延迟线，延迟线控制块和共享移位寄存器块。 时钟延迟线延迟输入时钟并产生延迟时钟。 命令延迟线延迟命令信号并产生延迟命令信号。 延迟线控制块根据比较由延迟时钟延迟建模延迟值和输入时钟而产生的反馈时钟的相位的结果产生控制信号。 响应于控制信号，共享移位寄存器块将时钟延迟线和命令延迟线的延迟量设定为彼此基本相同。

    Delay control circuit and clock generation circuit including the same
    20.
    发明授权
    Delay control circuit and clock generation circuit including the same 有权
    延迟控制电路和时钟发生电路包括相同

    公开(公告)号：US08754686B2

    公开(公告)日：2014-06-17

    申请号：US13711750

    申请日：2012-12-12

    Applicant: SK hynix Inc.

    Inventor： Dae Han Kwon ,  Yong Ju Kim ,  Jae Min Jang ,  Hae Rang Choi

    IPC: H03L7/06

    CPC classification number: H03L7/085 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/093 ,  H03L7/095 ,  H03L7/10

    Abstract: A clock generation circuit includes a delay line, which delays an input clock and generates a delayed clock, a delay modeling unit, which delays the delayed clock by a modeled delay value and generates a feedback clock, a phase detection unit, which compares phases of the input clock and the feedback clock and generates a phase detection signal, a filter unit, which receives the phase detection signal and generates phase information, generates an update signal when a difference between the numbers of phase detection signals with a first and a second level generated is greater than or equal to a threshold value, and generates the update signal after a lapse of a predetermined time when the difference is less than the threshold value, and a delay line control unit, which sets a delay value of the delay line in response to the update signal and the phase information.

    Abstract translation: 时钟生成电路包括延迟输入时钟并产生延迟时钟的延迟线，延迟建模单元，其通过建模延迟值延迟延迟时钟并产生反馈时钟;相位检测单元，其将 输入时钟和反馈时钟，并产生相位检测信号，滤波器单元，其接收相位检测信号并产生相位信息，当相位检测信号的数量与第一和第二电平之间的差异产生更新信号 产生的阈值大于或等于阈值，并且在差小于阈值的经过预定时间之后生成更新信号;以及延迟线控制单元，其将延迟线的延迟值设置在 对更新信号和相位信息的响应。

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