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    Majority decision circuit
    12.
    发明授权
    Majority decision circuit 有权
    多数决策电路

    公开(公告)号：US09054697B2

    公开(公告)日：2015-06-09

    申请号：US13890802

    申请日：2013-05-09

    Applicant: SK hynix Inc.

    Inventor： Hae-Rang Choi ,  Yong-Ju Kim ,  Oh-Kyong Kwon ,  Kang-Sub Kwak ,  Jun-Yong Song ,  Hyeon-Cheon Seol

    IPC: H03K19/23 ,  H03K19/003 ,  H03K19/08

    CPC classification number: H03K19/0813 ,  H03K19/23

    Abstract: A majority decision circuit includes: a majority decision unit configured to compare first data with second data to decide whether one of the first data and the second data has more bits with a first logical value; and an offset application unit configured to control the majority decision unit so that the majority decision unit decides, in a case when the number of bits with the first logical value among the first data is equal to the number of bits with the first logical value among the second data, that the first data have more bits with the first logical value if offset is a first setting value in a first phase and decides that the second data have more bits with the first logical value if the offset is a second setting value in a second phase.

    Abstract translation: 多数决定电路包括：多数决定单元，被配置为将第一数据与第二数据进行比较，以确定第一数据和第二数据之一是否具有更多具有第一逻辑值的位; 以及偏移应用单元，被配置为控制多数决定单元，使得多数决定单元在第一数据中具有第一逻辑值的比特数等于具有第一逻辑值的比特数在 第二数据，如果偏移量是第一相位中的第一设定值，则第一数据具有具有第一逻辑值的更多位，并且如果偏移量是第二设定值，则判定第二数据具有第一逻辑值的更多位 第二阶段

    Duty cycle correction circuit and operation method thereof
    13.
    发明授权
    Duty cycle correction circuit and operation method thereof 有权
    占空比校正电路及其操作方法

    公开(公告)号：US09018994B2

    公开(公告)日：2015-04-28

    申请号：US13844928

    申请日：2013-03-16

    Applicant: SK Hynix Inc.

    Inventor： Shin-Deok Kang ,  Jae-Min Jang ,  Yong-Ju Kim ,  Hae-Rang Choi

    IPC: H03K5/04 ,  H03K5/156

    CPC classification number: H03K3/017 ,  H03K5/1565

    Abstract: A duty cycle correction circuit includes a clock adjustment unit configured to adjust a duty ratio of an input clock signal in response to a duty control signal and generate an output clock signal, a tracking type setting unit configured to generate an tracking type selection signal for setting a first or second tracking type based on a duty locking state of the output clock signal, and a control signal generation unit configured to generate the duty control signal, into which the first or second tracking type is incorporated, in response to the tracking type selection signal and the output clock signal.

    Abstract translation: 占空比校正电路包括：时钟调整单元，被配置为响应于占空比控制信号调整输入时钟信号的占空比并产生输出时钟信号;跟踪类型设置单元，被配置为产生用于设置的跟踪类型选择信号 基于输出时钟信号的占空比锁定状态的第一或第二跟踪类型，以及控制信号生成单元，被配置为响应于跟踪类型选择生成并入第一或第二跟踪类型的占空比控制信号 信号和输出时钟信号。

    Memory system and method for operating the same
    14.
    发明授权
    Memory system and method for operating the same 有权

    公开(公告)号：US10346301B2

    公开(公告)日：2019-07-09

    申请号：US15653990

    申请日：2017-07-19

    Applicant: SK hynix Inc.

    Inventor： Sang-Gu Jo ,  Yong-Ju Kim

    IPC: G06F12/0804 ,  G06F12/06 ,  G06F13/16 ,  G11C11/34 ,  G11C11/407 ,  G11C29/44 ,  G11C29/00

    Abstract: A memory system includes: a memory device; and a memory controller suitable for controlling the memory device, and the memory device includes: a plurality of normal memory cells; a plurality of redundant memory cells; and a soft repair circuit suitable for replacing a portion of normal memory cells among the plurality of the normal memory cells with the plurality of the redundant memory cells, and the memory controller controls the soft repair circuit to repair the portion of the normal memory cells among the plurality of the normal memory cells with the plurality of the redundant memory cells, commands the memory device to write a secure data in the plurality of the redundant memory cells, and controls the soft repair circuit to recover the repairing of the portion of the normal memory cells with the plurality of the redundant memory cells.

    Memory device using extra read and write commands
    15.
    发明授权
    Memory device using extra read and write commands 有权

    公开(公告)号：US10114587B2

    公开(公告)日：2018-10-30

    申请号：US15148911

    申请日：2016-05-06

    Applicant: SK hynix Inc.

    Inventor： Young-Ook Song ,  Ki-Joong Kim ,  Jung-Hyun Kwon ,  Yong-Ju Kim

    IPC: G06F3/06 ,  G06F13/16 ,  G06F13/00

    Abstract: A memory device may include one or more multi-channel memories and an interface unit suitable for interfacing the multi-channel memories. The interface unit may include a first data interface suitable for transferring data for the first channel of the multi-channel memories, a second data interface suitable for transferring data for the second channel of the multi-channel memories, and an extra data interface suitable for transferring data for a selected one of the first channel and the second channel so that the data is additionally transmitted.

    Signal transfer circuit and operating method thereof
    17.
    发明授权
    Signal transfer circuit and operating method thereof 有权
    信号传输电路及其操作方法

    公开(公告)号：US09424894B2

    公开(公告)日：2016-08-23

    申请号：US14505115

    申请日：2014-10-02

    Applicant: SK hynix Inc.

    Inventor： Youk-Hee Kim ,  Yong-Ju Kim

    IPC: H03K3/00 ,  G11C7/10

    CPC classification number: G11C7/1078 ,  G11C7/106 ,  G11C7/1084 ,  G11C7/1087

    Abstract: A signal transfer circuit includes a signal input unit suitable for generating an input signal corresponding to a first voltage level and a second voltage level, a transfer control unit suitable for controlling a driving path of a transfer node in response to a control signal and selectively driving the transfer node to the second voltage level or a third voltage level, which is higher than the first voltage level, based on the driving path in response to the input signal, and an output control unit suitable for outputting an output signal by driving an output node based on a voltage level of the transfer node or maintaining a previous voltage level of the output node in response to the control signal.

    Abstract translation: 信号传输电路包括适于产生对应于第一电压电平和第二电压电平的输入信号的信号输入单元，适于响应于控制信号控制传输节点的驱动路径并选择性驱动的传送控制单元 基于响应于输入信号的驱动路径而将传输节点转换到第二电压电平或高于第一电压电平的第三电压电平，以及输出控制单元，其适于通过驱动输出来输出输出信号 基于传输节点的电压电平或者响应于控制信号保持输出节点的先前电压电平。

    Data recovery circuit and operating method thereof
    19.
    发明授权
    Data recovery circuit and operating method thereof 有权
    数据恢复电路及其操作方法

    公开(公告)号：US09018991B2

    公开(公告)日：2015-04-28

    申请号：US14106817

    申请日：2013-12-15

    Applicant: SK Hynix Inc. ,  Industry-University Cooperation Foundation Hanyang University

    Inventor： Hae-Rang Choi ,  Yong-Ju Kim ,  Oh-Kyong Kwon ,  Kang-Sub Kwak ,  Jun-Yong Song ,  Hyeon-Cheon Seol

    IPC: H03L7/06 ,  H03L7/08

    CPC classification number: H03L7/0807 ,  H04L7/0337 ,  H04L7/044

    Abstract: A data recovery circuit may include a data sampling unit suitable for sampling source data including an edge data using data clocks and an edge clock, a data extraction unit suitable for extracting the edge data from sampled data outputted from the data sampling unit, a control signal generation unit suitable for generating a phase control signal in response to the edge data, and a multi-clock control unit suitable for controlling phases of the data clocks and the edge clock in response to the phase control signal.

    Abstract translation: 数据恢复电路可以包括适于使用数据时钟和边沿时钟对包括边缘数据的源数据进行采样的数据采样单元，适合于从数据采样单元输出的采样数据中提取边缘数据的数据提取单元，控制信号 适用于响应于边缘数据产生相位控制信号的多时钟单元，以及适于根据相位控制信号控制数据时钟和边沿时钟的相位的多时钟控制单元。

    Memory system and operating method thereof
    20.
    发明授权
    Memory system and operating method thereof 有权

    公开(公告)号：US10445005B2

    公开(公告)日：2019-10-15

    申请号：US15726460

    申请日：2017-10-06

    Applicant: SK hynix Inc.

    Inventor： Do-Sun Hong ,  Yong-Ju Kim ,  Dong-Gun Kim

    IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02

    Abstract: A memory system includes a wear-leveling module detecting a hot memory block among a plurality of memory blocks based on the number of times write operations are performed on each of the memory blocks, and moving data from the hot memory block to a spare memory block, a counting unit counting the number of data movement from the hot memory block to the spare memory block, on each of memory regions formed by grouping the plurality of memory blocks, and output data movement counts, a first detection unit selecting one from the plurality of memory regions based on the data movement count, and detecting a cold memory block among memory blocks included in the selected memory region, and a management unit moving data from the cold memory block to the hot memory block, and managing the cold memory block as the spare memory block.

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