公开(公告)号：US20170084478A1

公开(公告)日：2017-03-23

申请号：US15264821

申请日：2016-09-14

Applicant: Soitec ,  Peregrine Semiconductor Corporation

Inventor： Bich-Yen Nguyen ,  Christophe Maleville ,  Sinan Goktepeli ,  Anthony Mark Miscione ,  Alain Duvallet

IPC: H01L21/763 ,  H01L23/66 ,  H01L21/762 ,  H01L21/02 ,  H01L29/04 ,  H01L29/16

CPC classification number: H01L21/763 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/7624 ,  H01L21/76254 ,  H01L23/66 ,  H01L27/13 ,  H01L29/04 ,  H01L29/16

Abstract: The invention relates to a structure for radiofrequency applications comprising: a monocrystalline substrate, a polycrystalline silicon layer directly on the monocrystalline substrate, and an active layer on the polycrystalline silicon layer intended to receive radiofrequency components. At least a first portion of the polycrystalline silicon layer extending from the interface of the polycrystalline silicon layer with the monocrystalline layer includes carbon and/or nitrogen atoms located at the grain boundaries of the polycrystalline silicon at a concentration of between 2% and 20%. A process for manufacturing such a structure includes, during deposition of at least a first portion of such a polycrystalline silicon layer located at the interface with the monocrystalline substrate, depositing carbon and/or atoms in the portion.

公开(公告)号：US11876020B2

公开(公告)日：2024-01-16

申请号：US17250767

申请日：2019-09-03

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Ludovic Ecarnot ,  Nicolas Daval ,  Bich-Yen Nguyen ,  Guillaume Besnard

IPC: H01L21/762 ,  H01L21/8238 ,  H01L21/324

CPC classification number: H01L21/823821 ,  H01L21/3247 ,  H01L21/7624

Abstract: A method for manufacturing a CFET device comprises forming a substrate of the double semi-conductor on insulator type, successively comprising, from the base to the surface thereof: a carrier substrate, a first electrically insulating layer, a first single-crystal semiconductor layer, a second electrically insulating layer and a second single-crystal semiconductor layer. Slices are formed into the substrate to the first electrically insulating layer so as to form at least one fin (F). A channel of a first transistor is formed in the first semiconductor layer and a channel of a second transistor is formed opposite the first transistor in the second semiconductor layer. Formation of the substrate of the double semi-conductor on insulator type comprises: a first and a second step of transferring a layer and thermal processing at a temperature that is sufficiently high to smooth the first single-crystal semiconductor layer to a roughness lower than 0.1 nm RMS.

公开(公告)号：US11156778B2

公开(公告)日：2021-10-26

申请号：US16323238

申请日：2017-07-27

Applicant: Soitec

Inventor： Bich-Yen Nguyen ,  Gweltaz Gaudin

IPC: H01L21/76 ,  G02B6/132 ,  G02B6/136 ,  H01L21/762

Abstract: A method for manufacturing a semiconductor structure or a photonic device, wherein the method comprises the steps of: providing a silicon nitride patterned layer over a carrier substrate; providing a first layer of a conformal oxide on the silicon nitride patterned layer such that it fully covers the silicon nitride patterned layer; and planarizing the first layer of conformal oxide to a predetermined thickness above the silicon nitride patterned layer to form a planarizing oxide layer. After the step of planarizing the first layer of conformal oxide, the method further comprises steps of clearing the silicon nitride patterned layer to form a dished silicon nitride patterned layer with a dishing height; and subsequently providing a second layer of a conformal oxide on or over the dished silicon nitride layer.

公开(公告)号：US11114314B2

公开(公告)日：2021-09-07

申请号：US16305695

申请日：2017-05-24

Applicant: Soitec

Inventor： Bich-Yen Nguyen ,  Ludovic Ecarnot ,  Nadia Ben Mohamed ,  Christophe Malville

IPC: H01L21/56 ,  H01L21/48 ,  H01L21/78

Abstract: A method of forming a semiconductor structure includes introducing, at selected conditions, hydrogen and helium species (e.g., ions) in a temporary support to form a plane of weakness at a predetermined depth therein, and to define a superficial layer and a residual part of the temporary support; forming on the temporary support an interconnection layer; placing at least one semiconductor chip on the interconnection layer; assembling a stiffener on a back side of the at least one semiconductor chip; and providing thermal energy to the temporary support to detach the residual part and provide the semiconductor structure. The interconnection layer forms an interposer free from any through via.

公开(公告)号：US20210202326A1

公开(公告)日：2021-07-01

申请号：US17250767

申请日：2019-09-03

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Ludovic Ecarnot ,  Nicolas Daval ,  Bich-Yen Nguyen ,  Guillaume Besnard

IPC: H01L21/8238 ,  H01L21/762 ,  H01L21/324

Abstract: A method for manufacturing a CFET device comprises forming a substrate of the double semi-conductor on insulator type, successively comprising, from the base to the surface thereof: a carrier substrate, a first electrically insulating layer, a first single-crystal semiconductor layer, a second electrically insulating layer and a second single-crystal semiconductor layer. Slices are formed into the substrate to the first electrically insulating layer so as to form at least one fin (F). A channel of a first transistor is formed in the first semiconductor layer and a channel of a second transistor is formed opposite the first transistor in the second semiconductor layer. Formation of the substrate of the double semi-conductor on insulator type, comprises: a first and a second step of transferring a layer and thermal processing at a temperature that is sufficiently high to smooth the first single-crystal semiconductor layer to a roughness lower than 0.1 nm RMS.

公开(公告)号：US20200295138A1

公开(公告)日：2020-09-17

申请号：US16086275

申请日：2017-03-31

Applicant: Soitec

Inventor： Christophe Figuet ,  Ludovic Ecarnot ,  Bich-Yen Nguyen ,  Walter Schwarzenbach ,  Daniel Delprat ,  Ionut Radu

IPC: H01L29/161 ,  H01L23/00

Abstract: A method for manufacturing a structure comprising a first substrate comprising at least one electronic component likely to be damaged by a temperature higher than 400° C. and a semiconductor layer extending on the first comprises: (a) providing a first bonding metal layer on the first substrate, (b) providing a second substrate comprising successively: a semiconductor base substrate, a stack of a plurality of semiconductor epitaxial layers, a layer of SixGe1-x, with 0≤x≤1 being located at the surface of said stack opposite to the base substrate, and a second bonding metal layer, (c) bonding the first substrate and the second substrate through the first and second bonding metal layers at a temperature lower than or equal to 400° C., and (d) removing a part of the second substrate so as to transfer the layer of SixGe1-x on the first substrate using a selective etching process.

公开(公告)号：US09818874B2

公开(公告)日：2017-11-14

申请号：US15161994

申请日：2016-05-23

Applicant: Soitec

Inventor： Bich-Yen Nguyen ,  Mariam Sadaka ,  Christophe Maleville

IPC: H01L29/66 ,  H01L23/52 ,  H01L21/46 ,  H01L21/4763 ,  H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L21/306 ,  H01L21/265 ,  H01L21/22 ,  H01L27/088 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/08 ,  H01L29/161 ,  H01L21/762 ,  H01L21/8234

CPC classification number: H01L29/7848 ,  H01L21/02002 ,  H01L21/22 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/76254 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/785

Abstract: Methods of forming a semiconductor structure include providing a multi-layer substrate having an epitaxial base layer overlying a strained primary semiconductor layer above a buried oxide layer. Elements within the epitaxial base layer are used to alter a strain state in the primary semiconductor layer within a first region of the multi-layer substrate without altering a strain state in the primary semiconductor layer within a second region of the multi-layer substrate. A first plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the first region of the multi-layer substrate, and a second plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the second region of the multi-layer substrate. Semiconductor structures fabricated by such methods may include transistor channel structures having differing strain states.

公开(公告)号：US09349865B2

公开(公告)日：2016-05-24

申请号：US14938545

申请日：2015-11-11

Applicant: Soitec

Inventor： Bich-Yen Nguyen ,  Mariam Sadaka ,  Christophe Maleville

IPC: H01L29/66 ,  H01L23/52 ,  H01L27/12 ,  H01L29/78 ,  H01L27/092 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/02002 ,  H01L21/22 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/76254 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/785

Abstract: Methods of forming a semiconductor structure include providing a multi-layer substrate having an epitaxial base layer overlying a strained primary semiconductor layer above a buried oxide layer. Elements within the epitaxial base layer are used to alter a strain state in the primary semiconductor layer within a first region of the multi-layer substrate without altering a strain state in the primary semiconductor layer within a second region of the multi-layer substrate. A first plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the first region of the multi-layer substrate, and a second plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the second region of the multi-layer substrate. Semiconductor structures fabricated by such methods may include transistor channel structures having differing strain states.

公开(公告)号：US20160086974A1

公开(公告)日：2016-03-24

申请号：US14830332

申请日：2015-08-19

Applicant: Soitec

Inventor： Mariam Sadaka ,  Bich-Yen Nguyen ,  Ionut Radu

IPC: H01L27/12 ,  H01L29/78 ,  H01L27/092 ,  H01L29/16 ,  H01L29/161

CPC classification number: H01L27/1203 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/84 ,  H01L21/845 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/1211 ,  H01L29/16 ,  H01L29/161 ,  H01L29/7847

Abstract: Methods of fabricating a semiconductor structure include implanting ion into a second region of a strained semiconductor layer on a multi-layer substrate to amorphize a portion of crystalline semiconductor material in the second region of the strained semiconductor layer without amorphizing a first region of the strained semiconductor layer. The amorphous region is recrystallized, and elements are diffused within the semiconductor layer to enrich a concentration of the diffused elements in a portion of the second region of the strained semiconductor layer and alter a strain state therein relative to a strain state of the first region of the strained semiconductor layer. A first plurality of transistor channel structures are formed that each comprise a portion of the first region of the semiconductor layer, and a second plurality of transistor channel structures are formed that each comprise a portion of the second region of the semiconductor layer.

Abstract translation: 制造半导体结构的方法包括将离子注入到多层衬底上的应变半导体层的第二区域中，以使应变半导体层的第二区域中的部分晶体半导体材料非晶化，而不会使应变半导体的第一区域失活 层。 非晶区域被重结晶，并且元件在半导体层内扩散以富集在应变半导体层的第二区域的一部分中的扩散元件的浓度，并且相对于第一区域的第一区域的应变状态改变其中的应变状态 应变半导体层。 形成第一多个晶体管沟道结构，每个晶体管沟道结构各自包括半导体层的第一区域的一部分，并且形成第二多个晶体管沟道结构，每个晶体管沟道结构各自包括半导体层的第二区域的一部分。

公开(公告)号：US09209301B1

公开(公告)日：2015-12-08

申请号：US14489841

申请日：2014-09-18

Applicant: Soitec

Inventor： Bich-Yen Nguyen ,  Walter Schwarzenbach ,  Christophe Maleville

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/12 ,  H01L21/265 ,  H01L21/02 ,  H01L29/16 ,  H01L29/32 ,  H01L21/84

CPC classification number: H01L21/2253 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02617 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/76251 ,  H01L21/76281 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/32 ,  H01L29/7849

Abstract: Methods of fabricating a semiconductor structure include providing a semiconductor-on-insulator (SOI) substrate including a base substrate, a strained stressor layer above the base substrate, a surface semiconductor layer, and a dielectric layer between the stressor layer and the surface semiconductor layer. Ions are implanted into or through a first region of the stressor layer, and additional semiconductor material is formed on the surface semiconductor layer above the first region of the stressor layer. The strain state in the first region of the surface semiconductor layer above the first region of the stressor layer is altered, and a trench structure is formed at least partially into the base substrate. The strain state is altered in a second region of the surface semiconductor layer above the second region of the stressor layer. Semiconductor structures are fabricated using such methods.

Abstract translation: 制造半导体结构的方法包括提供包括基底基板，在基底基板上方的应变应力层，表面半导体层和应力层与表面半导体层之间的电介质层的绝缘体上半导体 。 离子被注入或穿过应力层的第一区域，并且在应力层的第一区域上方的表面半导体层上形成附加的半导体材料。 在应力层的第一区域上方的表面半导体层的第一区域中的应变状态被改变，并且沟槽结构至少部分地形成到基底衬底中。 在应力层的第二区域上方的表面半导体层的第二区域中改变应变状态。 使用这种方法制造半导体结构。