公开(公告)号：US12232435B2

公开(公告)日：2025-02-18

申请号：US18130184

申请日：2023-04-03

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Franck Arnaud ,  David Galpin ,  Stephane Zoll ,  Olivier Hinsinger ,  Laurent Favennec ,  Jean-Pierre Oddou ,  Lucile Broussous ,  Philippe Boivin ,  Olivier Weber ,  Philippe Brun ,  Pierre Morin

IPC: H10B63/00 ,  G11C13/00 ,  H10N70/00 ,  H10N70/20

Abstract: An integrated circuit includes a substrate with an active area, a first insulating layer, a second insulating layer, and a phase-change material. The integrated circuit further includes a heating element in an L-shape, with a long side in direct physical contact with the phase-change material and a short side in direct physical contact with a via. The heating element is surrounded by first, second, and third insulating spacers, with the first insulating spacer having a planar first sidewall in contact with the long side of the heating element, a convex second sidewall, and a planar bottom face in contact with the short side of the heating element. The second and third insulating spacers are in direct contact with the first insulating spacer and the long side of the heating element.

公开(公告)号：US10510955B2

公开(公告)日：2019-12-17

申请号：US15953921

申请日：2018-04-16

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics S.r.l.

Inventor： Pierre Morin ,  Michel Haond ,  Paola Zuliani

IPC: H01L45/00 ,  H01L27/24

Abstract: A phase change memory includes an L-shaped resistive element having a first part that extends between a layer of phase change material and an upper end of a conductive via and a second part that rests at least partially on the upper end of the conductive via and may further extend beyond a peripheral edge of the conductive via. The upper part of the conductive via is surrounded by an insulating material that is not likely to adversely react with the metal material of the resistive element.

公开(公告)号：US20170194498A1

公开(公告)日：2017-07-06

申请号：US15387712

申请日：2016-12-22

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Remy Berthelon ,  Didier Dutartre ,  Pierre Morin ,  Francois Andrieu ,  Elise Baylac

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/7849 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/76281 ,  H01L21/76283 ,  H01L29/66477 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/78684

Abstract: A strained semiconductor layer is produced from a semiconductor layer extending on an insulating layer. A thermal oxidization is performed on the semiconductor layer across its entire thickness to form two bars extending in a direction of a transistor width. Insulating trenches are formed in a direction of a transistor length. A strain of the strained semiconductor layer is induced in one implementation before the thermal oxidation is performed. Alternatively, the strain is induced after the thermal oxidation is performed. The insulating trenches serve to release a component of the strain extending in the direction of transistor width. A component of the strain extending in the direction of transistor length is maintained. The bars and trenches delimit an active area of the transistor include source, drain and channel regions.

公开(公告)号：US09269768B2

公开(公告)日：2016-02-23

申请号：US14605064

申请日：2015-01-26

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： David Barge ,  Pierre Morin

IPC: H01L29/06 ,  H01L21/762 ,  H01L27/12

CPC classification number: H01L29/0653 ,  H01L21/76283 ,  H01L27/1203

Abstract: An insulation wall separating transistors formed in a thin semiconductor layer resting on an insulating layer laid on a semiconductor substrate, this wall being formed of an insulating material and comprising a wall crossing the thin layer and the insulating layer and penetrating into the substrate, and lateral extensions extending in the substrate under the insulating layer.

公开(公告)号：US10483393B2

公开(公告)日：2019-11-19

申请号：US15798976

申请日：2017-10-31

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Pierre Morin

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/165 ,  H01L29/15 ,  H01L29/16 ,  H01L29/161

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

公开(公告)号：US20160133692A1

公开(公告)日：2016-05-12

申请号：US14982474

申请日：2015-12-29

Applicant: STMicroelectronics, Inc. ,  Commissariat a I'energie Atomique et Aux Energies Alternatives ,  GlobalFoundries Inc.

Inventor： Pierre Morin ,  Maud Vinet ,  Laurent Grenouillet ,  Ajey Poovannummoottil Jacob

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/02 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/283 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0607 ,  H01L21/02636 ,  H01L21/283 ,  H01L21/3086 ,  H01L21/32 ,  H01L21/762 ,  H01L21/76264 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0665 ,  H01L29/1066 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7847 ,  H01L29/7849

Abstract: Methods and structures for forming uniaxially-strained, nanoscale, semiconductor bars from a biaxially-strained semiconductor layer are described. A spatially-doubled mandrel process may be used to form a mask for patterning dense, narrow trenches through the biaxially-strained semiconductor layer. The resulting slicing of the biaxially-strained layer enhances carrier mobility and can increase device performance.

Abstract translation: 描述了从双轴应变半导体层形成单轴应变纳米级半导体条的方法和结构。 可以使用空间双倍的心轴工艺来形成用于图案化通过双轴应变半导体层的致密的窄沟槽的掩模。 所得到的双轴应变层的切片增强了载流子迁移率并且可以提高器件性能。

公开(公告)号：US09331175B2

公开(公告)日：2016-05-03

申请号：US14452041

申请日：2014-08-05

Applicant: STMicroelectronics SA ,  STMicroelectronics, Inc.

Inventor： Pierre Morin ,  Denis Rideau ,  Olivier Nier

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/02 ,  H01L21/324 ,  H01L21/762 ,  H01L29/78 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L29/66772 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/324 ,  H01L21/76283 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7847

Abstract: The disclosure concerns a method of stressing a semiconductor layer comprising: depositing, over a semiconductor on insulator (SOI) structure having a semiconductor layer in contact with an insulating layer, a stress layer; locally stressing said semiconductor layer by forming one or more openings in said stress layer, said openings being aligned with first regions of said semiconductor layer in which transistor channels are to be formed; and deforming second regions of said insulating layer adjacent to said first regions by temporally decreasing, by annealing, the viscosity of said insulator layer.

Abstract translation: 本公开涉及一种应力半导体层的方法，包括：在绝缘体上半导体层（SOI）结构上沉积，该结构具有与绝缘层接触的半导体层，应力层; 通过在所述应力层中形成一个或多个开口来对所述半导体层进行局部应力，所述开口与要形成晶体管沟道的所述半导体层的第一区对齐; 以及通过退火所述绝缘体层的粘度暂时减小所述绝缘层的与所述第一区域相邻的第二区域。

公开(公告)号：US09287130B1

公开(公告)日：2016-03-15

申请号：US14676345

申请日：2015-04-01

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Xiuyu Cai ,  Ajey Poovannummoottil Jacob ,  Ruilong Xie ,  Bruce Doris ,  Kangguo Cheng ,  Jason R. Cantone ,  Sylvie Mignot ,  David Moreau ,  Muthumanickam Sankarapandian ,  Pierre Morin ,  Su Chen Fan ,  Kisik Choi ,  Murat K. Akarvardar

IPC: H01L21/00 ,  H01L21/308 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/266

CPC classification number: H01L21/823431 ,  H01L21/30604 ,  H01L21/845 ,  H01L29/66795

Abstract: A method includes forming a plurality of fin elements above a substrate. A mask is formed above the substrate. The mask has an opening defined above at least one selected fin element of the plurality of fin elements. An ion species is implanted into the at least one selected fin element through the opening to increase its etch characteristics relative to the other fin elements. The at least one selected fin element is removed selectively relative to the other fin elements.

Abstract translation: 一种方法包括在基底上形成多个翅片元件。 在基板上形成掩模。 掩模具有限定在多个翅片元件中的至少一个选定翅片元件上方的开口。 通过开口将离子物质注入到至少一个选定的翅片元件中，以相对于其它翅片元件增加其蚀刻特性。 选择性地将至少一个选定的翅片元件相对于其它翅片元件移除。

公开(公告)号：US09236474B2

公开(公告)日：2016-01-12

申请号：US14186342

申请日：2014-02-21

Applicant: STMicroelectronics, Inc.

Inventor： Pierre Morin

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/12

CPC classification number: H01L29/7848 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7846 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/78654

Abstract: Methods and structures for forming strained-channel FETs are described. A strain-inducing layer may be formed under stress in a silicon-on-insulator substrate below the insulator. Stress-relief cuts may be formed in the strain-inducing layer to relieve stress in the strain-inducing layer. The relief of stress can impart strain to an adjacent semiconductor layer. Strained-channel, fully-depleted SOI FETs and strained-channel finFETs may be formed from the adjacent semiconductor layer. The amount and type of strain may be controlled by etch depths and geometries of the stress-relief cuts and choice of materials for the strain-inducing layer.

Abstract translation: 描述形成应变通道FET的方法和结构。 应变诱导层可以在绝缘体下方的绝缘体上硅衬底中的应力下形成。 可以在应变诱导层中形成应力消除切口以减轻应变诱导层中的应力。 应力的解除可以使相邻的半导体层产生应变。 可以从相邻的半导体层形成应变通道，完全耗尽的SOI FET和应变通道的finFET。 应变的量和类型可以通过蚀刻深度和应力消除切割的几何形状以及用于应变诱导层的材料的选择来控制。

公开(公告)号：US09219133B2

公开(公告)日：2015-12-22

申请号：US13905586

申请日：2013-05-30

Applicant: STMICROELECTRONICS, INC.

Inventor： Nicolas Loubet ,  Pierre Morin

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/06

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/66439 ,  H01L29/66795

Abstract: A method of making a semiconductor device includes forming a first spacer for at least one gate stack on a first semiconductor material layer, and forming a respective second spacer for each of source and drain regions adjacent the at least one gate. Each second spacer has a pair of opposing sidewalls and an end wall coupled thereto. The method includes filling the source and drain regions with a second semiconductor material while the first and second spacers provide confinement.

Abstract translation: 制造半导体器件的方法包括在第一半导体材料层上形成用于至少一个栅极叠层的第一间隔物，以及与邻近所述至少一个栅极的每个源区和漏区形成相应的第二间隔物。 每个第二间隔件具有一对相对的侧壁和与其连接的端壁。 该方法包括用第二半导体材料填充源区和漏区，而第一和第二间隔件提供约束。