公开(公告)号：US20160042955A1

公开(公告)日：2016-02-11

申请号：US14923176

申请日：2015-10-26

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT ,  STMICROELECTRONICS (Crolles 2) SAS

Inventor： Heimanu NIEBOJEWSKI ,  Yves Morand ,  Maud Vinet

IPC: H01L21/28 ,  H01L21/762 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L21/28123 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02645 ,  H01L21/02667 ,  H01L21/76205 ,  H01L21/7624 ,  H01L21/76248 ,  H01L21/84 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78603

Abstract: The invention relates to a method for manufacturing a transistor comprising the preparation of a stack of layers of the semiconductor on insulator type comprising at least one substrate on which an insulating layer and an initial semiconductor layer are successively disposed. The method includes the formation of at least one oxide pad extending from a top face of the insulating layer, the formation of an additional layer made from semiconductor material covering the oxide pad and intended to form a channel for the transistor, the formation of a gate stack above the oxide pad, and the formation of a source and drain on either side of the gate stack.

Abstract translation: 本发明涉及一种晶体管的制造方法，其包括制备绝缘体上半导体层的一叠叠层，其中至少一个衬底上依次配置绝缘层和初始半导体层。 该方法包括形成从绝缘层的顶面延伸的至少一个氧化物焊盘，形成由半导体材料制成的附加层，该半导体材料覆盖氧化物焊盘并且旨在形成用于晶体管的沟道，形成栅极 堆叠在氧化物垫的上方，并且在栅极堆叠的任一侧上形成源极和漏极。

公开(公告)号：US09911820B2

公开(公告)日：2018-03-06

申请号：US15464763

申请日：2017-03-21

Applicant: Commissariat a l'energie atomique et aux energies alternatives ,  STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Cyrille Le Royer ,  Frederic Boeuf ,  Laurent Grenouillet ,  Louis Hutin ,  Yves Morand

IPC: H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L23/535 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L29/4983 ,  H01L21/76895 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/66628

Abstract: A method of fabrication, including the steps for supplying a substrate including a layer of semiconductor material covered by a sacrificial gate including a sacrificial gate insulator including a middle part, and edges covered by sacrificial spacers and having a thickness tox; removal of the sacrificial gate insulator and the sacrificial gate material; formation of a conformal deposition of thickness thk of dielectric material inside of the groove formed in order to form a gate insulator, with tox>thk≧tox/2; formation of a gate electrode within the groove; removal of the sacrificial spacers so as to open up edges of the gate insulator layer; formation of spacers on the edges of the gate insulator layer on either side of the gate electrode, these spacers having a dielectric constant at the most equal to 3.5.

公开(公告)号：US20150091089A1

公开(公告)日：2015-04-02

申请号：US14499545

申请日：2014-09-29

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Heimanu Niebojewski ,  Yves Morand ,  Cyrille Le Royer ,  Olivier Rozeau

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/515 ,  H01L29/0843 ,  H01L29/4983 ,  H01L29/4991 ,  H01L29/51 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/78

Abstract: A MOS transistor has a gate insulator layer that is made of a material of high dielectric constant deposited on a substrate. The gate insulator layer extends, with a constant thickness, under and beyond a gate stack. Spacers of low dielectric constant are formed on either side of the gate stack and vertically separated from the substrate by the extension of the gate insulator layer beyond the sides of the gate stack. The spacers of low dielectric constant are preferably air spacers.

Abstract translation: MOS晶体管具有由沉积在衬底上的高介电常数材料制成的栅极绝缘体层。 栅极绝缘体层以恒定的厚度延伸到栅极堆叠之下和之外。 通过栅极绝缘体层的延伸超过栅极叠层的侧面，在栅极叠层的任一侧上形成具有低介电常数的隔板并与衬底垂直分离。 低介电常数的间隔物优选为空气间隔物。

公开(公告)号：US08980702B2

公开(公告)日：2015-03-17

申请号：US14177614

申请日：2014-02-11

Applicant: Commissariat a l'Energie Atomique et aux ene Alt ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Heimanu Niebojewski ,  Yves Morand ,  Maud Vinet

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78603

Abstract: A method for manufacturing a transistor includes forming a stack of semiconductor on insulator type layers including at least one substrate, surmounted by a first insulating layer and an active layer to form a channel for the transistor; forming a gate stack on the active layer; producing a source and a drain including forming, on either side of the gate stack, cavities by at least one step of etching the active layer, the first insulating layer, and part of the substrate selectively to the gate stack to remove the active layer, the first insulating layer, and a portion of the substrate outside regions situated below the gate stack; forming a second insulating layer on the bared surfaces of the substrate, to form a continuous insulating layer with the first insulating layer; baring of the lateral ends of the channel; and the filling of the cavities by epitaxy.

Abstract translation: 一种制造晶体管的方法，包括：形成绝缘体上半导体层的叠层，其包括至少一个衬底，其被第一绝缘层和有源层所覆盖以形成晶体管的沟道; 在有源层上形成栅叠层; 产生源极和漏极，包括在栅叠层的任一侧通过至少一个步骤，至少一个步骤，将有源层，第一绝缘层和衬底的一部分选择性地栅极堆叠以形成去除有源层， 所述第一绝缘层和位于所述栅叠层下方的所述衬底外部区域的一部分; 在所述基板的裸露表面上形成第二绝缘层，以形成具有所述第一绝缘层的连续绝缘层; 通道的横向端部露出; 并通过外延填充空腔。

公开(公告)号：US09978602B2

公开(公告)日：2018-05-22

申请号：US14923176

申请日：2015-10-26

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT ,  STMICROELECTRONICS (Crolles 2) SAS ,  STMICROELECTRONICS SA

Inventor： Heimanu Niebojewski ,  Yves Morand ,  Maud Vinet

IPC: H01L21/84 ,  H01L21/28 ,  H01L29/66 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L21/28123 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02645 ,  H01L21/02667 ,  H01L21/76205 ,  H01L21/7624 ,  H01L21/76248 ,  H01L21/84 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78603

Abstract: The invention relates to a method for manufacturing a transistor comprising the preparation of a stack of layers of the semiconductor on insulator type comprising at least one substrate on which an insulating layer and an initial semiconductor layer are successively disposed. The method includes the formation of at least one oxide pad extending from a top face of the insulating layer, the formation of an additional layer made from semiconductor material covering the oxide pad and intended to form a channel for the transistor, the formation of a gate stack above the oxide pad, and the formation of a source and drain on either side of the gate stack.

公开(公告)号：US20170186623A1

公开(公告)日：2017-06-29

申请号：US15390077

申请日：2016-12-23

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Nicolas POSSEME ,  Maxime Garcia-Barros ,  Yves Morand

IPC: H01L21/324 ,  H01L21/322 ,  H01L29/78 ,  H01L21/02 ,  H01L21/447 ,  H01L21/762 ,  H01L21/223

CPC classification number: H01L21/324 ,  H01L21/02057 ,  H01L21/223 ,  H01L21/2236 ,  H01L21/31155 ,  H01L21/3221 ,  H01L21/447 ,  H01L21/762 ,  H01L21/823468 ,  H01L29/4908 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7827

Abstract: There is provided a method for manufacturing a transistor from a stack including at least one gate pattern comprising at least one flank, the method including forming at least one gate spacer over at least the flank of the gate pattern; and reducing, after a step of exposure of the stack to a temperature greater than or equal to 600° C., of a dielectric permittivity of the at least one gate spacer, the reducing including at least one ion implantation in a portion at least of a thickness of the at least one gate spacer.

公开(公告)号：US09117805B2

公开(公告)日：2015-08-25

申请号：US14169913

申请日：2014-01-31

Applicant: STMicroelectronics S.A. ,  STMicroelectronics (Crolles 2) SAS ,  Commissariat à l'Énergie Atomique et aux Énergies Alternatives

Inventor： Heimanu Niebojewski ,  Yves Morand ,  Cyrille Le Royer

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/49 ,  H01L29/423

CPC classification number: H01L29/49 ,  H01L21/28008 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4925 ,  H01L29/4991 ,  H01L29/6653

Abstract: A MOS transistor including, above a gate insulator, a conductive gate stack having a height, a length, and a width, this stack having a lower portion close to the gate insulator and an upper portion, wherein the stack has a first length in its lower portion, and a second length shorter than the first length in its upper portion.

Abstract translation: 一种MOS晶体管，包括在栅极绝缘体上方的具有高度，长度和宽度的导电栅极堆叠，该堆叠具有靠近栅绝缘体的下部和上部，其中堆叠具有第一长度 下部，并且在其上部比第一长度短的第二长度。

公开(公告)号：US20140370666A1

公开(公告)日：2014-12-18

申请号：US14177593

申请日：2014-02-11

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT ,  STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Maud VINET ,  Yves Morand ,  Heimanu Niebojewski

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L29/66477 ,  H01L21/02236 ,  H01L21/02667 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/7624 ,  H01L21/76248 ,  H01L21/76272 ,  H01L21/76278 ,  H01L21/84 ,  H01L27/1207

Abstract: A method is provided for producing a semiconductor layer having at least two different thicknesses from a stack of the semiconductor on insulator type including at least one substrate on which an insulating layer and a first semiconductor layer are successively disposed, the method including etching the first layer so that said layer is continuous and includes at least one first region having a thickness less than that of at least one second region; oxidizing the first layer to form an electrically insulating oxide film on a surface thereof so that, in the first region, the oxide film extends as far as the insulating layer; partly removing the oxide film to bare the first layer outside the first region; forming a second semiconductor layer on the stack, to form, with the first layer, a third continuous semiconductor layer having a different thickness than that of the first and second regions.

Abstract translation: 提供一种用于制造半导体层的半导体层的方法，所述半导体层具有至少两个不同厚度的绝缘体上的半导体层，包括至少一个其上连续设置有绝缘层和第一半导体层的基板，所述方法包括蚀刻第一层 使得所述层是连续的并且包括至少一个具有小于至少一个第二区域的厚度的第一区域; 氧化第一层以在其表面上形成电绝缘氧化膜，使得在第一区域中，氧化膜延伸至绝缘层; 部分地除去氧化膜以露出第一区域外的第一层; 在所述堆叠上形成第二半导体层，以与所述第一层形成具有与所述第一和第二区域的厚度不同的厚度的第三连续半导体层。

公开(公告)号：US08895420B2

公开(公告)日：2014-11-25

申请号：US14040270

申请日：2013-09-27

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Daniel-Camille Bensahel ,  Yves Morand

IPC: H01L29/36 ,  H01L21/22 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/306 ,  H01L29/66

CPC classification number: H01L21/22 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/36 ,  H01L29/66659

Abstract: A semiconductive device is fabricated by forming, within a semiconductive substrate, at least one continuous region formed of a material having a non-uniform composition in a direction substantially perpendicular to the thickness of the substrate.

Abstract translation: 半导体器件通过在半导体衬底内形成至少一个由具有基本上垂直于衬底厚度的方向上具有不均匀组成的材料形成的连续区域来制造。

公开(公告)号：US20140335663A1

公开(公告)日：2014-11-13

申请号：US14177614

申请日：2014-02-11

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT ,  STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Heimanu NIEBOJEWSKI ,  Yves Morand ,  Maud Vinet

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78603

Abstract: A method for manufacturing a transistor includes forming a stack of semiconductor on insulator type layers including at least one substrate, surmounted by a first insulating layer and an active layer to form a channel for the transistor; forming a gate stack on the active layer; producing a source and a drain including forming, on either side of the gate stack, cavities by at least one step of etching the active layer, the first insulating layer, and part of the substrate selectively to the gate stack to remove the active layer, the first insulating layer, and a portion of the substrate outside regions situated below the gate stack; forming a second insulating layer on the bared surfaces of the substrate, to form a continuous insulating layer with the first insulating layer; baring of the lateral ends of the channel; and the filling of the cavities by epitaxy.

Abstract translation: 一种制造晶体管的方法，包括：形成绝缘体上半导体层的叠层，其包括至少一个衬底，其被第一绝缘层和有源层所覆盖以形成晶体管的沟道; 在有源层上形成栅叠层; 产生源极和漏极，包括在栅叠层的任一侧通过至少一个步骤，至少一个步骤，将有源层，第一绝缘层和衬底的一部分选择性地栅极堆叠以形成去除有源层， 所述第一绝缘层和位于所述栅叠层下方的所述衬底外部区域的一部分; 在所述基板的裸露表面上形成第二绝缘层，以形成具有所述第一绝缘层的连续绝缘层; 通道的横向端部露出; 并通过外延填充空腔。