公开(公告)号：US09911827B2

公开(公告)日：2018-03-06

申请号：US15372930

申请日：2016-12-08

Applicant: Commissariat a l'energie atomique et aux energies alternatives ,  STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Louis Hutin ,  Julien Borrel ,  Yves Morand ,  Fabrice Nemouchi

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L29/66643 ,  H01L29/0895 ,  H01L29/66636 ,  H01L29/7839

Abstract: A process for manufacturing a Schottky barrier field-effect transistor is provided. The process includes: providing a structure including a control gate and a semiconductive layer positioned under the gate and having protrusions that protrude laterally with respect to the gate; anisotropically etching at least one of the protrusions by using the control gate as a mask, so as to form a recess in this protrusion, this recess defining a lateral face of the semiconductive layer; depositing a layer of insulator on the lateral face of the semiconductive layer; and depositing a metal in the recess on the layer of insulator so as to form a contact of metal/insulator/semiconductor type between the deposit of metal and the lateral face of the semiconductive layer.

公开(公告)号：US20170271470A1

公开(公告)日：2017-09-21

申请号：US15464763

申请日：2017-03-21

Applicant: Commissariat a l'energie atomique et aux energies alternatives ,  STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Cyrille LE ROYER ,  Frederic Boeuf ,  Laurent Grenouillet ,  Louis Hutin ,  Yves Morand

IPC: H01L29/49 ,  H01L21/768 ,  H01L29/06 ,  H01L29/66 ,  H01L29/51 ,  H01L23/535

CPC classification number: H01L29/4983 ,  H01L21/76895 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/66628

Abstract: A method of fabrication, including the steps for supplying a substrate including a layer of semiconductor material covered by a sacrificial gate including a sacrificial gate insulator including a middle part, and edges covered by sacrificial spacers and having a thickness tox; removal of the sacrificial gate insulator and the sacrificial gate material; formation of a conformal deposition of thickness thk of dielectric material inside of the groove formed in order to form a gate insulator, with tox>thk≧tox/2; formation of a gate electrode within the groove; removal of the sacrificial spacers so as to open up edges of the gate insulator layer; formation of spacers on the edges of the gate insulator layer on either side of the gate electrode, these spacers having a dielectric constant at the most equal to 3.5.

公开(公告)号：US09502558B2

公开(公告)日：2016-11-22

申请号：US14791713

申请日：2015-07-06

Applicant: Commissariat a L'Energie Atomique et aux Energies Alternatives ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Shay Reboh ,  Laurent Grenouillet ,  Cyrille Le Royer ,  Sylvain Maitrejean ,  Yves Morand

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L29/7847 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02667 ,  H01L21/26506 ,  H01L29/66477 ,  H01L29/66772 ,  H01L29/7849

Abstract: Method to strain a channel zone of a transistor of the semiconductor on insulator type transistor that makes use of an SMT stress memorization technique in which regions located under the insulation layer of the substrate (FIG. 6) are amorphized, before the transistor gate is made.

Abstract translation: 使用在晶体管栅极制造之前利用其中位于衬底（图6）的绝缘层下方的区域非晶化的SMT应力存储技术的半导体绝缘体型晶体管的晶体管的沟道区域的方法 。

公开(公告)号：US09269570B2

公开(公告)日：2016-02-23

申请号：US13860845

申请日：2013-04-11

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Yves Morand ,  Charles Baudot ,  Fabrice Nemouchi

IPC: H01L21/02 ,  H01L21/285

CPC classification number: H01L21/02381 ,  H01L21/28518

Abstract: A method is provided for producing a microelectronic device with plural zones made of a metal and semiconductor compound, from semiconductor zones made of different semiconductor materials, and on which a thin semiconductor layer is formed prior to the deposition of a metal layer so as to lower the nucleation barrier of the semiconductor zones when reacting with the metal layer.

Abstract translation: 提供了一种从由不同半导体材料制成的半导体区域制造具有由金属和半导体化合物制成的多个区域的微电子器件的方法，并且在沉积金属层之前在其上形成薄的半导体层以便降低 当与金属层反应时，半导体区的成核势垒。

公开(公告)号：US08962399B2

公开(公告)日：2015-02-24

申请号：US14177593

申请日：2014-02-11

Applicant: Commissariat a l'Energie Atomique et aux Ene Alt ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Maud Vinet ,  Yves Morand ,  Heimanu Niebojewski

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/762

CPC classification number: H01L29/66477 ,  H01L21/02236 ,  H01L21/02667 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/7624 ,  H01L21/76248 ,  H01L21/76272 ,  H01L21/76278 ,  H01L21/84 ,  H01L27/1207

Abstract: A method is provided for producing a semiconductor layer having at least two different thicknesses from a stack of the semiconductor on insulator type including at least one substrate on which an insulating layer and a first semiconductor layer are successively disposed, the method including etching the first layer so that said layer is continuous and includes at least one first region having a thickness less than that of at least one second region; oxidizing the first layer to form an electrically insulating oxide film on a surface thereof so that, in the first region, the oxide film extends as far as the insulating layer; partly removing the oxide film to bare the first layer outside the first region; forming a second semiconductor layer on the stack, to form, with the first layer, a third continuous semiconductor layer having a different thickness than that of the first and second regions.

Abstract translation: 提供一种用于制造半导体层的半导体层的方法，所述半导体层具有至少两个不同厚度的绝缘体上的半导体层，包括至少一个其上连续设置有绝缘层和第一半导体层的基板，所述方法包括蚀刻第一层 使得所述层是连续的并且包括至少一个具有小于至少一个第二区域的厚度的第一区域; 氧化第一层以在其表面上形成电绝缘氧化膜，使得在第一区域中，氧化膜延伸至绝缘层; 部分地除去氧化膜以露出第一区域外的第一层; 在所述堆叠上形成第二半导体层，以与所述第一层形成具有与所述第一和第二区域的厚度不同的厚度的第三连续半导体层。

公开(公告)号：US10658197B2

公开(公告)日：2020-05-19

申请号：US15390077

申请日：2016-12-23

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Nicolas Posseme ,  Maxime Garcia-Barros ,  Yves Morand

IPC: H01L21/324 ,  H01L21/3115 ,  H01L21/02 ,  H01L21/223 ,  H01L21/322 ,  H01L21/447 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78

Abstract: There is provided a method for manufacturing a transistor from a stack including at least one gate pattern comprising at least one flank, the method including forming at least one gate spacer over at least the flank of the gate pattern; and reducing, after a step of exposure of the stack to a temperature greater than or equal to 600° C., of a dielectric permittivity of the at least one gate spacer, the reducing including at least one ion implantation in a portion at least of a thickness of the at least one gate spacer.

公开(公告)号：US09240325B2

公开(公告)日：2016-01-19

申请号：US14498091

申请日：2014-09-26

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS SA ,  STMICROELECTRONICS (Crolles 2) SAS

Inventor： Sébastien Barnola ,  Yves Morand ,  Heimanu Niebojewski

IPC: H01L29/423 ,  H01L29/78 ,  H01L21/283 ,  H01L29/66 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L29/42372 ,  H01L21/28008 ,  H01L21/28052 ,  H01L21/28123 ,  H01L21/283 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/45 ,  H01L29/49 ,  H01L29/4933 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78

Abstract: A method includes making a gate stack on the surface of an active zone, including depositing a first dielectric layer; depositing a gate conductive layer; depositing a first metal layer; depositing a second metal layer; depositing a second dielectric layer; partially etching the gate stack for the formation of a gate zone on the active zone; making insulating spacers on either side of the gate zone on the active zone; making source and drain electrodes zones; making silicidation zones on the surface of the source and drain zones; etching, in the gate zone on the active zone, the second dielectric layer and the second metal layer with stopping on the first metal layer, so as to form a cavity between the insulating spacers; making a protective plug at the surface of the first metal layer of the gate zone on the active zone, where the protective plug fills the cavity.

Abstract translation: 一种方法包括在有源区的表面上形成栅极堆叠，包括沉积第一介电层; 沉积栅极导电层; 沉积第一金属层; 沉积第二金属层; 沉积第二电介质层; 部分地蚀刻栅极堆叠以在有源区上形成栅极区; 在活动区域​​上的栅极区域的任一侧上制造绝缘垫片; 制造源极和漏极区域; 在源极和漏极区域的表面上形成硅化物区域; 在活性区域的栅极区域中蚀刻在第一金属层上停止的第二介电层和第二金属层，以在绝缘间隔物之间​​形成空腔; 在活动区域​​上的栅极区域的第一金属层的表面上形成保护塞，其中保护塞填充空腔。

公开(公告)号：US20140217520A1

公开(公告)日：2014-08-07

申请号：US14169913

申请日：2014-01-31

Applicant: STMicroelectronics S.A. ,  STMicroelectronics (Crolles 2) SAS ,  Commissariat à I'Énergie Atomique et aux Énergies Alternatives

Inventor： Heimanu Niebojewski ,  Yves Morand ,  Cyrille Le Royer

IPC: H01L29/49 ,  H01L21/28

CPC classification number: H01L29/49 ,  H01L21/28008 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4925 ,  H01L29/4991 ,  H01L29/6653

Abstract: A MOS transistor including, above a gate insulator, a conductive gate stack having a height, a length, and a width, this stack having a lower portion close to the gate insulator and an upper portion, wherein the stack has a first length in its lower portion, and a second length shorter than the first length in its upper portion.

Abstract translation: 一种MOS晶体管，包括在栅极绝缘体上方的具有高度，长度和宽度的导电栅极堆叠，该堆叠具有靠近栅绝缘体的下部和上部，其中堆叠具有第一长度 下部，并且在其上部比第一长度短的第二长度。

公开(公告)号：US09425255B2

公开(公告)日：2016-08-23

申请号：US14982852

申请日：2015-12-29

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Sylvain Barraud ,  Yves Morand

IPC: H01L29/06 ,  H01L21/84 ,  H01L51/05 ,  H01L29/41 ,  H01L51/44 ,  H01L29/786 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0669 ,  H01L29/413 ,  H01L29/785 ,  H01L29/78648 ,  H01L29/78696 ,  H01L51/057 ,  H01L51/444 ,  H01L2924/13061 ,  H01L2924/13086

Abstract: Fabrication of a microelectronic device on a semiconductor on insulator type substrate, the device being provided with a transistor of a given type, the channel structure of which is formed from semiconducting bar(s), a dielectric area different from the insulating layer of the substrate being provided to replace the insulating layer, facing the transistor channel structure, specifically for this given type of transistor.

Abstract translation: 在半导体绝缘体型衬底上制造微电子器件，该器件设置有给定类型的晶体管，其沟道结构由半导体棒形成，不同于衬底的绝缘层的电介质区域 被提供以替代面向晶体管沟道结构的绝缘层，具体用于该给定类型的晶体管。

公开(公告)号：US09276073B2

公开(公告)日：2016-03-01

申请号：US14266999

申请日：2014-05-01

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Sylvain Barraud ,  Yves Morand

IPC: H01L21/84 ,  H01L29/06 ,  H01L29/41 ,  H01L51/05 ,  H01L51/44 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L29/0673 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0669 ,  H01L29/413 ,  H01L29/785 ,  H01L29/78648 ,  H01L29/78696 ,  H01L51/057 ,  H01L51/444 ,  H01L2924/13061 ,  H01L2924/13086

Abstract: Fabrication of a microelectronic device on a semiconductor on insulator type substrate, the device being provided with a transistor of a given type, the channel structure of which is formed from semiconducting bar(s), a dielectric area different from the insulating layer of the substrate being provided to replace the insulating layer, facing the transistor channel structure, specifically for this given type of transistor.