公开(公告)号：US09691866B2

公开(公告)日：2017-06-27

申请号：US15252090

申请日：2016-08-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Arnaud Regnier ,  Jean-Michel Mirabel ,  Stephan Niel ,  Francesco La Rosa

IPC: H01L29/423 ,  H01L27/11524 ,  H01L29/788 ,  H01L29/78 ,  G11C16/04 ,  H01L29/66 ,  H01L27/11521

CPC classification number: H01L29/42336 ,  G11C16/0433 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7831 ,  H01L29/7881 ,  H01L29/7885 ,  H01L29/7889

Abstract: A memory cell formed in a semiconductor substrate, includes a selection gate extending vertically in a trench made in the substrate, and isolated from the substrate by a first layer of gate oxide, a horizontal floating gate extending above the substrate and isolated from the substrate by a second layer of gate oxide, and a horizontal control gate extending above the floating gate. The selection gate covers a lateral face of the floating gate. The floating gate is separated from the selection gate only by the first layer of gate oxide, and separated from a vertical channel region, extending in the substrate along the selection gate, only by the second layer of gate oxide.

公开(公告)号：US09627068B2

公开(公告)日：2017-04-18

申请号：US14980853

申请日：2015-12-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: G11C16/04 ,  G11C16/08 ,  G11C7/18 ,  H01L27/11519 ,  H01L27/11524 ,  G11C16/26 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02

CPC classification number: G11C16/26 ,  G11C7/18 ,  G11C16/0408 ,  G11C16/0433 ,  G11C16/08 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/42324

Abstract: Non-volatile memory including rows and columns of memory cells, the columns of memory cells including pairs of twin memory cells including a common selection gate. According to the disclosure, two bitlines are provided per column of memory cells. The adjacent twin memory cells of the same column are not connected to the same bitline while the adjacent non-twin memory cells of the same column are connected to the same bitline.

公开(公告)号：US09627011B1

公开(公告)日：2017-04-18

申请号：US15212211

申请日：2016-07-16

Applicant: STMicroelectronics S.r.l ,  STMicroelectronics (Rousset) SAS

Inventor： Antonino Conte ,  Francesco La Rosa

IPC: G11C7/02 ,  G11C7/08 ,  G11C7/12

CPC classification number: G11C7/08 ,  G11C7/062 ,  G11C7/12 ,  G11C16/28 ,  H03F3/45475 ,  H03F3/45968 ,  H03F2203/45212

Abstract: A method for operating a non-volatile memory device uses a sense amplifier that includes a first branch and a second branch. During a pre-charging step, a bit line of a memory array of the non-volatile memory device is biased in order to pre-charge the bit line. During the pre-charging step, an offset between the first branch and the second branch is detected and stored. During a reading step subsequent to the pre-charging step, a cell current is received from the bit line at the first branch and a reference current is received from a current-reference structure at the second branch. During the reading step, and amplified voltage is generated as a function of the cell current and the reference current. During the reading step, an output voltage is generated based on the amplified voltage compensated by the offset stored during the pre-charging step.

公开(公告)号：US09484107B2

公开(公告)日：2016-11-01

申请号：US14724229

申请日：2015-05-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: G11C11/34 ,  G11C16/06 ,  G11C16/26 ,  G11C16/04 ,  H01L27/115 ,  H01L21/28 ,  H01L21/027 ,  G11C16/14 ,  H01L27/02

CPC classification number: G11C16/26 ,  G11C16/0408 ,  G11C16/0433 ,  G11C16/0441 ,  G11C16/08 ,  G11C16/14 ,  H01L21/0276 ,  H01L21/28273 ,  H01L27/0207 ,  H01L27/11521 ,  H01L27/11524

Abstract: The present disclosure relates to a non-volatile memory cell on a semiconductor substrate, comprising a first transistor comprising a control gate, a floating gate and a drain region, a second transistor comprising a control gate, a floating gate and a drain region, in which the floating gates of the first and second transistors are electrically coupled, and the second transistor comprises a conducting region electrically coupled to its drain region and extending opposite its floating gate through a tunnel dielectric layer.

Abstract translation: 本公开涉及一种半导体衬底上的非易失性存储单元，包括：第一晶体管，包括控制栅极，浮置栅极和漏极区域;第二晶体管，包括控制栅极，浮置栅极和漏极区域， 其中第一和第二晶体管的浮置栅极电耦合，并且第二晶体管包括电耦合到其漏极区域并且通过隧道电介质层与其浮动栅极相对延伸的导电区域。

公开(公告)号：US09443598B2

公开(公告)日：2016-09-13

申请号：US14719913

申请日：2015-05-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: G11C16/04 ,  G11C16/14 ,  H01L27/115

CPC classification number: G11C16/14 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/0458 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11517

Abstract: The present disclosure relates to a method for controlling two twin memory cells each comprising a floating-gate transistor comprising a state control gate, in series with a select transistor comprising a select control gate common to the two memory cells, the drains of the floating-gate transistors being connected to a same bit line, the method comprising steps of programming the first memory cell by hot-electron injection, by applying a positive voltage to the bit line and a positive voltage to the state control gate of the first memory cell, and simultaneously, of applying to the state control gate of the second memory cell a positive voltage capable of causing a programming current to pass through the second memory cell, without switching it to a programmed state.

Abstract translation: 本公开涉及一种用于控制两个双存储单元的方法，每个双存储器单元包括浮置晶体管，其包括状态控制栅极，与包括两个存储单元共用的选择控制栅极的选择晶体管串联， 栅极晶体管连接到相同的位线，该方法包括以下步骤：通过对位线施加正电压并将正电压施加到第一存储单元的状态控制栅极，通过热电子注入来对第一存储单元进行编程， 并且同时向第二存储单元的状态控制栅极施加能够使编程电流通过第二存储单元的正电压，而不将其切换到编程状态。

公开(公告)号：US09224482B2

公开(公告)日：2015-12-29

申请号：US14528780

申请日：2014-10-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier ,  Julien Delalleau

IPC: G11C16/00 ,  G11C16/10 ,  G11C16/34 ,  G11C16/04 ,  H01L29/788 ,  H01L27/115 ,  H01L29/423

CPC classification number: G11C16/10 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/34 ,  G11C16/3418 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/7881

Abstract: The present disclosure relates to a memory comprising at least one word line comprising a row of split gate memory cells each comprising a selection transistor section comprising a selection gate and a floating-gate transistor section comprising a floating gate and a control gate. According to the present disclosure, the memory comprises a source plane common to the memory cells of the word line, to collect programming currents passing through memory cells during their programming, and the selection transistor sections of the memory cells are connected to the source plane. A programming current control circuit is configured to control the programming current passing through the memory cells by acting on a selection voltage applied to a selection line.

Abstract translation: 本公开涉及包括至少一个字线的存储器，该字线包括一行分离栅极存储单元，每行分离栅极存储单元包括选择晶体管部分，该选择晶体管部分包括选择栅极和包括浮置栅极和控制栅极的浮动栅极晶体管部分。 根据本公开，存储器包括与字线的存储器单元共同的源平面，以在编程期间收集通过存储器单元的编程电流，并且存储器单元的选择晶体管部分连接到源极平面。 编程电流控制电路被配置为通过作用于施加到选择线的选择电压来控制通过存储器单元的编程电流。

公开(公告)号：US09091713B2

公开(公告)日：2015-07-28

申请号：US13669732

申请日：2012-11-06

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa

IPC: G01R27/02 ,  G01R27/26 ,  G06F3/041 ,  G06F3/044

CPC classification number: G01R27/2605 ,  G06F3/0416 ,  G06F3/044

Abstract: A method for characterizing or measuring a capacitance includes linking the capacitance to a first mid-point of a first capacitive divider bridge, applying to the divider bridge a bias voltage, maintaining the voltage of the first mid-point near a reference voltage, discharging a second mid-point of a second divider bridge in parallel with the first using a constant current, and measuring the time for a voltage of the second mid-point to become equal to the voltage of the first mid-point. The method may be applied in particular to the control of a touch screen display.

Abstract translation: 用于表征或测量电容的方法包括将电容连接到第一电容性分压器桥的第一中点，向分压器桥施加偏置电压，将第一中点的电压维持在参考电压附近， 第二分频桥的第二中点与第一分频桥并联，使用恒定电流，并且测量第二中点的电压的时间变得等于第一中点的电压。 该方法可以特别地应用于触摸屏显示器的控制。

公开(公告)号：US20150043269A1

公开(公告)日：2015-02-12

申请号：US14494095

申请日：2014-09-23

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Pascal Fornara

IPC: G01R27/26 ,  G11C11/24 ,  H01G4/018 ,  G01R17/02 ,  H01G4/38 ,  H01G4/005

CPC classification number: G01R27/2605 ,  G01R17/02 ,  G04F10/10 ,  G04F13/00 ,  G11C11/24 ,  G11C27/024 ,  H01G4/005 ,  H01G4/018 ,  H01G4/38 ,  H01L21/84 ,  H01L23/5223 ,  H01L27/0805 ,  H01L27/1203 ,  H01L28/40 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A charge flow circuit for a time measurement, including a plurality of elementary capacitive elements electrically in series, each elementary capacitive element leaking through its dielectric space.

Abstract translation: 一种用于时间测量的电荷流动电路，包括电串联的多个基本电容元件，每个元件电容元件通过其介电空间泄漏。

公开(公告)号：US12143108B2

公开(公告)日：2024-11-12

申请号：US17812127

申请日：2022-07-12

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics International N.V.

Inventor： Francesco La Rosa ,  Marco Bildgen

IPC: H03K19/17768 ,  H03K19/08 ,  H03K19/1776 ,  H04L9/32

Abstract: In an embodiment an integrated device includes a first physical unclonable function module configured to generate an initial data group and management module configured to generate an output data group from at least the initial data group, authorize only D successive deliveries of the output data group on a first output interface of the device, D being a non-zero positive integer, and prevent any new generation of the output data group.

公开(公告)号：US12125533B2

公开(公告)日：2024-10-22

申请号：US17812122

申请日：2022-07-12

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics International N.V.

Inventor： Francesco La Rosa ,  Marco Bildgen

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H10B41/35

CPC classification number: G11C16/0433 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H10B41/35

Abstract: In an embodiment a non-volatile memory device includes a memory plane including at least one memory area including an array of memory cells having two rows and N columns, wherein each memory cell comprises a state transistor having a control gate and a floating gate selectable by a vertical selection transistor buried in a substrate and including a buried selection gate, and wherein each column of memory cells includes a pair of twin memory cells, two selection transistors of the pair of twin memory cells having a common selection gate and a processing device configured to store in the memory area information including a succession of N bits so that, with exception of the last bit of the succession, a current bit of the succession is stored in two memory cells located on the same row and on two adjacent columns and a current bit and the following bit are respectively stored in two twin cells.