中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

22 records (took 0.029 seconds)

    Self-calibrated digital-to-analog converter
    13.
    发明授权
    Self-calibrated digital-to-analog converter 有权
    自校准数模转换器

    公开(公告)号：US09379728B1

    公开(公告)日：2016-06-28

    申请号：US14751456

    申请日：2015-06-26

    Applicant: STMicroelectronics International N.V.

    Inventor： Pratap Narayan Singh ,  Shiva Sharath Babu Kaleru ,  Ankur Bal ,  Mohit Singh ,  Rakesh Malik

    IPC: H03M1/10 ,  H03M1/74

    CPC classification number: H03M1/1023 ,  H03M1/1047 ,  H03M1/66

    Abstract: A digital-to-analog converter has an output. An analog-to-digital converter senses a voltage at the output of the digital-to-analog converter and generates a digital voltage signal. A source mismatch estimator processes the digital voltage signal to output an error signal indicative of current source mismatch within the digital-to-analog converter. An error code generator generates a digital calibration signal from the error signal. The digital calibration signal is converted by a redundancy digital-to-analog converter to an analog compensation signal for application to the output of analog-to-digital converter to nullify effects of the current source mismatch.

    Abstract translation: 一个数模转换器有一个输出。 模拟 - 数字转换器感测数模转换器输出端的电压，并产生一个数字电压信号。 源不匹配估计器处理数字电压信号以输出指示数模转换器内的电流源失配的误差信号。 错误代码发生器从误差信号产生数字校准信号。 数字校准信号由冗余数模转换器转换为模拟补偿信号，以应用于模数转换器的输出，以消除电流源不匹配的影响。

    ADAPTIVE DELAY BASED ASYNCHRONOUS SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER
    14.
    发明申请
    ADAPTIVE DELAY BASED ASYNCHRONOUS SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER 审中-公开
    基于自适应延迟的异步连续逼近模拟数字转换器

    公开(公告)号：US20160056830A1

    公开(公告)日：2016-02-25

    申请号：US14930708

    申请日：2015-11-03

    Applicant: STMicroelectronics International N.V.

    Inventor： Rakesh Malik ,  Chandrajit Debnath ,  Ashish Sharma Kumar ,  Pratap Narayan Singh

    IPC: H03M1/12 ,  H03M1/46 ,  H03M1/06

    CPC classification number: H03M1/125 ,  H03M1/00 ,  H03M1/0612 ,  H03M1/069 ,  H03M1/0695 ,  H03M1/12 ,  H03M1/46 ,  H03M1/462

    Abstract: An asynchronous SAR ADC converts an analog signal into a series of digital pulses in an efficient, low power manner. In synchronous SAR ADC circuits, a separate and cumbersome clock signal is used to trigger the internal circuitry of the SAR ADC. Instead of triggering the components of the SAR DAC synchronously with a clock signal, the asynchronous solution uses its own internal signals to trigger its components in an asynchronous cyclic manner. Further, in order to increase efficiency and guard against circuit failures due to difficulties arising from transient signals, the asynchronous SAR ADC may also include a delay circuit for introducing a variable delay to the SAR ADC cycle.

    Abstract translation: 异步SAR ADC以有效，低功耗的方式将模拟信号转换为一系列数字脉冲。 在同步SAR ADC电路中，单独和繁琐的时钟信号用于触发SAR ADC的内部电路。 异步解决方案不是以时钟信号同步触发SAR DAC的组件，而是以其自身的内部信号以异步循环方式触发其组件。 此外，为了提高效率并防止由于瞬态信号引起的困难而导致的电路故障，异步SAR ADC还可以包括用于将可变延迟引入SAR ADC周期的延迟电路。

    Circuit and method for skew correction
    15.
    发明授权
    Circuit and method for skew correction 有权
    用于偏斜校正的电路和方法

    公开(公告)号：US09000963B2

    公开(公告)日：2015-04-07

    申请号：US14293119

    申请日：2014-06-02

    Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

    Inventor： Pratap Narayan Singh ,  Stéphane Le Tual

    IPC: H03M1/00 ,  H03K17/22 ,  H03M1/12 ,  H03K17/14 ,  H03K17/687

    CPC classification number: H03K17/223 ,  H03K17/145 ,  H03K17/687 ,  H03K2217/0018 ,  H03M1/12

    Abstract: The invention concerns a circuit comprising: a first transistor (102) having first and second main current nodes, and a gate node adapted to receive a first timing signal (CLK) for causing the first transistor to transition between conducting and non-conducting states; a biasing circuit (108) coupled to a further node of said first transistor; and a control circuit (110) adapted to control said biasing circuit to apply a first control voltage (VCTRL) to said further node to adjust the timing of at least one of said transitions.

    Abstract translation: 本发明涉及一种电路，包括：具有第一和第二主电流节点的第一晶体管（102）和适于接收用于使第一晶体管在导通状态与非导通状态之间转变的第一定时信号（CLK）的栅极节点; 偏置电路（108），耦合到所述第一晶体管的另一节点; 以及适于控制所述偏置电路以对所述另一节点施加第一控制电压（VCTRL）以调整至少一个所述转换的定时的控制电路（110）。

    Variable Delay Element
    16.
    发明申请
    Variable Delay Element 有权
    可变延迟元件

    公开(公告)号：US20150028930A1

    公开(公告)日：2015-01-29

    申请号：US14337896

    申请日：2014-07-22

    Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

    Inventor： Stéphane Le Tual ,  Pratap Narayan Singh

    IPC: H03H11/26

    CPC classification number: H03K5/134 ,  H03K5/13 ,  H03K2005/00032 ,  H03K2005/00208 ,  H03K2005/00215 ,  H03K2217/0018

    Abstract: A delay circuit includes first and second transistors and a biasing circuit. The first transistor has a control node coupled to an input node of the delay circuit, a first main current node coupled to a first supply voltage, and a second main current node coupled to an output node of the delay circuit. A second transistor has a control node coupled to the input node, a first main current node coupled to a second supply voltage, and a second main current node coupled to the output node. The biasing circuit is configured to generate first and second differential control voltages , to apply the first differential control voltage to a further control node of the first transistor and to apply the second differential control voltage to a further control node of the second transistor.

    Abstract translation: 延迟电路包括第一和第二晶体管和偏置电路。 第一晶体管具有耦合到延迟电路的输入节点的控制节点，耦合到第一电源电压的第一主电流节点和耦合到延迟电路的输出节点的第二主电流节点。 第二晶体管具有耦合到输入节点的控制节点，耦合到第二电源电压的第一主电流节点和耦合到输出节点的第二主电流节点。 偏置电路被配置为产生第一和第二差分控制电压，以将第一差分控制电压施加到第一晶体管的另一控制节点，并将第二差分控制电压施加到第二晶体管的另一个控制节点。

    SUPPLY VOLTAGE COMPENSATION FOR AN INPUT/OUTPUT DRIVER CIRCUIT USING CLOCK SIGNAL FREQUENCY COMPARISON
    17.
    发明申请
    SUPPLY VOLTAGE COMPENSATION FOR AN INPUT/OUTPUT DRIVER CIRCUIT USING CLOCK SIGNAL FREQUENCY COMPARISON 审中-公开

    公开(公告)号：US20190074835A1

    公开(公告)日：2019-03-07

    申请号：US15698022

    申请日：2017-09-07

    Applicant: STMicroelectronics International N.V.

    Inventor： Prashant Singh ,  Pratap Narayan Singh

    IPC: H03K19/003 ,  H03K17/14 ,  H03K19/177

    Abstract: A process and temperature variation operating condition that is globally applicable to an integrated circuit die is sensed in a core circuit region to generate a global process and temperature compensation signal. A voltage variation operating condition that is locally applicable to an input/output circuit within a peripheral circuit region of the integrated circuit die is sensed to generate a local voltage compensation signal. More specifically, the localized voltage operating condition is generated as a function of a measured difference in frequency between a first clock signal generated in the peripheral circuit region in response to a supply voltage subject to voltage variation and a second clock signal generated in the core circuit region in response to a fixed bandgap reference voltage. The operation of the input/output circuit is then altered in response to the global process and temperature compensation signal and in response to the local voltage compensation signal.

Patent Agency Ranking