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    Semiconductor package, and package on package having the same
    11.
    发明授权
    Semiconductor package, and package on package having the same 有权

    公开(公告)号：US11581263B2

    公开(公告)日：2023-02-14

    申请号：US17024852

    申请日：2020-09-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Choongbin Yim ,  Jungwoo Kim ,  Jihwang Kim ,  Jungsoo Byun ,  Jongbo Shim ,  Doohwan Lee ,  Kyoungsei Choi ,  Junggon Choi ,  Sungeun Pyo

    IPC: H01L23/495 ,  H01L23/538 ,  H01L25/10

    Abstract: A semiconductor package includes: a redistribution layer including a plurality of redistribution insulating layers, a plurality of redistribution line patterns that constitute lower wiring layers, and a plurality of redistribution vias that are connected to some of the plurality of redistribution line patterns while penetrating at least one of the plurality of redistribution insulating layers; at least one semiconductor chip arranged on the redistribution layer; an expanded layer surrounding the at least one semiconductor chip on the redistribution layer; and a cover wiring layer including at least one base insulating layer, a plurality of wiring patterns that constitute upper wiring layers, and a plurality of conductive vias that are connected to some of the plurality of wiring patterns while penetrating the at least one base insulating layer.

    SEMICONDUCTOR PACKAGE
    15.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20230042622A1

    公开(公告)日：2023-02-09

    申请号：US17742819

    申请日：2022-05-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Choongbin Yim ,  Jihwang Kim ,  Jongbo Shim ,  Jinwoo Park

    IPC: H01L23/00 ,  H01L25/10 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

    Abstract: A semiconductor package includes a first package substrate having a lower surface and an upper surface respectively including a plurality of first lower surface pads and a plurality of first upper surface pads, a second package substrate having a lower surface and an upper surface respectively including a plurality of second lower surface pads and a plurality of second upper surface pads, wherein the plurality of second upper surface pads comprise all of the upper surface pads at the upper surface of the second package substrate, a semiconductor chip provided between the first package substrate and the second package substrate and attached onto the first package substrate, and a plurality of metal core structures connecting some of the plurality of first upper surface pads to some of the plurality of second lower surface pads and not vertically overlapping any of the plurality of second upper surface pads, each metal core structure having a metal core.

    Semiconductor package with interposer
    17.
    发明授权
    Semiconductor package with interposer 有权

    公开(公告)号：US11367688B2

    公开(公告)日：2022-06-21

    申请号：US17090502

    申请日：2020-11-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Choongbin Yim ,  Jungwoo Kim ,  Jihwang Kim ,  Jongbo Shim ,  Kyoungsei Choi

    IPC: H01L23/538 ,  H01L23/31 ,  H01L23/14

    Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a molding layer covering side walls of the first semiconductor chip and including through holes, an interposer on the first semiconductor chip and the molding layer, conductive connectors in the through holes of the molding layer and connected to the first package substrate and the interposer, and an insulating filler including a first portion that fills the through holes of the molding layer so as to surround side walls of the conductive connectors.

    SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME
    20.
    发明申请
    SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME 有权

    公开(公告)号：US20240404921A1

    公开(公告)日：2024-12-05

    申请号：US18439461

    申请日：2024-02-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Choongbin Yim ,  Chengtar Wu

    IPC: H01L23/482 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

    Abstract: A semiconductor package includes: a redistribution layer structure; first semiconductor and second dies on the redistribution, the second semiconductor die positioned next to the first semiconductor die; core balls positioned on the redistribution structure and next to the first semiconductor chip die; a bridge die configured to electrically connect the first and second semiconductor dies to each other on the first and second semiconductor dies; a substrate including an upper plate portion and a sidewall portion, the upper plate portion and the sidewall portion defining a cavity, the upper plate portion positioned on the bridge die, the side wall portion positioned on the core balls, the bridge die positioned within the cavity; and a molding material configured to mold the first semiconductor die, the second semiconductor die, the core balls, and the bridge die between the redistribution layer structure and the substrate.

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