公开(公告)号：US20170092769A1

公开(公告)日：2017-03-30

申请号：US15374093

申请日：2016-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghyun Roh ,  Pankwi Park ,  Dongsuk Shin ,  Chulwoong Lee ,  Naein Lee

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/306 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/7849 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/66477 ,  H01L29/66553 ,  H01L29/7848

Abstract: According to embodiments of the inventive concept, a gate electrode is formed on a substrate, and a first spacer, a second spacer, and a third spacer are sequentially formed on a sidewall of the gate electrode. The substrate is etched to form a recess region. A compressive stress pattern is formed in the recess region. A protective spacer is formed on a sidewall of the third spacer. When the recess region is formed, a lower portion of the second spacer is removed to form a gap region between the first and third spacers. The protective spacer fills the gap region.

公开(公告)号：US09299836B2

公开(公告)日：2016-03-29

申请号：US14626211

申请日：2015-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Hyuk Kim ,  Hoi Sung Chung ,  Dongsuk Shin ,  Naein Lee

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/165 ,  H01L29/04

CPC classification number: H01L29/7833 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66477 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device including source drain stressors and methods of manufacturing the same are provided. The methods may include forming a recess region in the substrate at a side of a gate pattern, and an inner surface of the recess region may include a first surface of a (100) crystal plane and a second surface of one of {111} crystal planes. The method may further include performing a first selective epitaxial growth (SEG) process to form a base epitaxial pattern on the inner surface of the recess region at a process pressure in a range of about 50 Torr to about 300 Torr. The method may also include performing a second selective epitaxial growth (SEG) process to form a bulk epitaxial pattern on the base epitaxial pattern.

Abstract translation: 提供了包括源漏应力源的半导体器件及其制造方法。 所述方法可以包括在栅极图案侧的基板中形成凹陷区域，并且凹部区域的内表面可以包括（100）晶面的第一表面和{111}晶体之一的第二表面 飞机 该方法还可以包括执行第一选择性外延生长（SEG）工艺，以在约50托至约300托的范围内的工艺压力下在凹陷区的内表面上形成基底外延图案。 该方法还可以包括执行第二选择性外延生长（SEG）工艺以在基底外延图案上形成体外延图案。

公开(公告)号：US09136176B2

公开(公告)日：2015-09-15

申请号：US14318957

申请日：2014-06-30

Applicant: SAMSUNG Electronics Co., Ltd.

Inventor： Dong Hyuk Kim ,  Dongsuk Shin ,  Myungsun Kim ,  Hoi Sung Chung

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L29/08 ,  H01L21/306 ,  H01L21/3065

CPC classification number: H01L29/7848 ,  H01L21/02057 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/088 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/45 ,  H01L29/66636

Abstract: A method of fabricating one or more semiconductor devices includes forming a trench in a semiconductor substrate, performing a cycling process to remove contaminants from the trench, and forming an epitaxial layer on the trench. The cycling process includes sequentially supplying a first reaction gas containing germane, hydrogen chloride and hydrogen and a second reaction gas containing hydrogen chloride and hydrogen onto the semiconductor substrate.

Abstract translation: 制造一个或多个半导体器件的方法包括在半导体衬底中形成沟槽，执行循环过程以从沟槽去除污染物，以及在沟槽上形成外延层。 循环过程包括将含有锗烷，氯化氢和氢的第一反应气体和含有氯化氢和氢的第二反应气体依次提供到半导体衬底上。

公开(公告)号：US20150179795A1

公开(公告)日：2015-06-25

申请号：US14626211

申请日：2015-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Hyuk KIM ,  Hoi Sung Chung ,  Dongsuk Shin ,  Naein Lee

IPC: H01L29/78 ,  H01L29/04

CPC classification number: H01L29/7833 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66477 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device including source drain stressors and methods of manufacturing the same are provided. The methods may include forming a recess region in the substrate at a side of a gate pattern, and an inner surface of the recess region may include a first surface of a (100) crystal plane and a second surface of one of {111} crystal planes. The method may further include performing a first selective epitaxial growth (SEG) process to form a base epitaxial pattern on the inner surface of the recess region at a process pressure in a range of about 50 Torr to about 300 Torr. The method may also include performing a second selective epitaxial growth (SEG) process to form a bulk epitaxial pattern on the base epitaxial pattern.

Abstract translation: 提供了包括源漏应力源的半导体器件及其制造方法。 所述方法可以包括在栅极图案侧的基板中形成凹陷区域，并且凹部区域的内表面可以包括（100）晶面的第一表面和{111}晶体之一的第二表面 飞机 该方法还可以包括执行第一选择性外延生长（SEG）工艺，以在约50托至约300托的范围内的工艺压力下在凹陷区的内表面上形成基底外延图案。 该方法还可以包括执行第二选择性外延生长（SEG）工艺以在基底外延图案上形成体外延图案。

公开(公告)号：US12249606B2

公开(公告)日：2025-03-11

申请号：US18414039

申请日：2024-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhee Choi ,  Keunhwi Cho ,  Myunggil Kang ,  Seokhoon Kim ,  Dongwon Kim ,  Pankwi Park ,  Dongsuk Shin

IPC: H01L27/092 ,  H01L21/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/167 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

Abstract: An integrated circuit device includes a fin-type active area along a first horizontal direction on a substrate, a device isolation layer on opposite sidewalls of the fin-type active area, a gate structure along a second horizontal direction crossing the first horizontal direction, the gate structure being on the fin-type active area and on the device isolation layer, and a source/drain area on the fin-type active area, the source/drain area being adjacent to the gate structure, and including an outer blocking layer, an inner blocking layer, and a main body layer sequentially stacked on the fin-type active area, and each of the outer blocking layer and the main body layer including a Si1-xGex layer, where x≠0, and the inner blocking layer including a Si layer.

公开(公告)号：US12142671B2

公开(公告)日：2024-11-12

申请号：US17514008

申请日：2021-10-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong Chan Suh ,  Sangmoon Lee ,  Yihwan Kim ,  Woo Bin Song ,  Dongsuk Shin ,  Seung Ryul Lee

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor device and a semiconductor device, the method including forming an active pattern on a substrate such that the active pattern includes sacrificial patterns and semiconductor patterns alternately and repeatedly stacked on the substrate; and forming first spacer patterns at both sides of each of the sacrificial patterns by performing an oxidation process, wherein the first spacer patterns correspond to oxidized portions of each of the sacrificial patterns, wherein the sacrificial patterns include a first semiconductor material containing impurities, wherein the semiconductor patterns include a second semiconductor material different from the first semiconductor material, and wherein the impurities include an element different from semiconductor elements of the first semiconductor material and the second semiconductor material.

公开(公告)号：US11631674B2

公开(公告)日：2023-04-18

申请号：US17231114

申请日：2021-04-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minhee Choi ,  Keunhwi Cho ,  Myunggil Kang ,  Seokhoon Kim ,  Dongwon Kim ,  Pankwi Park ,  Dongsuk Shin

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: An integrated circuit device includes a fin-type active area along a first horizontal direction on a substrate, a device isolation layer on opposite sidewalls of the fin-type active area, a gate structure along a second horizontal direction crossing the first horizontal direction, the gate structure being on the fin-type active area and on the device isolation layer, and a source/drain area on the fin-type active area, the source/drain area being adjacent to the gate structure, and including an outer blocking layer, an inner blocking layer, and a main body layer sequentially stacked on the fin-type active area, and each of the outer blocking layer and the main body layer including a Si1-xGex layer, where x≠0, and the inner blocking layer including a Si layer.

公开(公告)号：US11122513B2

公开(公告)日：2021-09-14

申请号：US16537869

申请日：2019-08-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghun Heo ,  Youngduk Kim ,  Joonseok Kim ,  Dongsuk Shin

IPC: H04W52/02 ,  G06F1/32

Abstract: A power management approach for a mobile device includes comparing a battery provided power supply voltage to a reference voltage in order to generate an alarm signal. In response to the alarm signal the frequency of an operating clock applied to a system-on-chip is changed.

公开(公告)号：US10692993B2

公开(公告)日：2020-06-23

申请号：US15956166

申请日：2018-04-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong Chan Suh ,  Sangmoon Lee ,  Yihwan Kim ,  Woo Bin Song ,  Dongsuk Shin ,  Seung Ryul Lee

IPC: H01L21/82 ,  H01L29/66 ,  H01L21/28 ,  H01L29/786 ,  H01L29/423 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor device and a semiconductor device, the method including forming an active pattern on a substrate such that the active pattern includes sacrificial patterns and semiconductor patterns alternately and repeatedly stacked on the substrate; and forming first spacer patterns at both sides of each of the sacrificial patterns by performing an oxidation process, wherein the first spacer patterns correspond to oxidized portions of each of the sacrificial patterns, wherein the sacrificial patterns include a first semiconductor material containing impurities, wherein the semiconductor patterns include a second semiconductor material different from the first semiconductor material, and wherein the impurities include an element different from semiconductor elements of the first semiconductor material and the second semiconductor material.

公开(公告)号：US09865698B2

公开(公告)日：2018-01-09

申请号：US15053842

申请日：2016-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Kwan Yu ,  Kooktae Kim ,  Chanjin Park ,  Dongsuk Shin ,  Youngdal Lim ,  Sahwan Hong

IPC: H01L27/108 ,  H01L29/49 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/4991 ,  H01L21/7682 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L23/485 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

Abstract: A semiconductor device includes a gate assembly disposed on a device isolation layer, a gate spacer disposed on a side surface of the gate assembly, a contact assembly disposed on the gate spacer, an air gap disposed between the device isolation layer and the contact assembly, and a first spacer capping layer disposed between the gate spacer and the air gap. The first spacer capping layer has an etch selectivity with respect to the gate spacer.