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公开(公告)号：US10127102B2
公开(公告)日：2018-11-13
申请号：US15229774
申请日：2016-08-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ye-Sin Ryu , Hoi-Ju Chung , Sang-Uhn Cha , Young-Yong Byun , Seong-Jin Jang
Abstract: A semiconductor memory device includes a memory cell array, a control logic circuit, an error correction circuit and a first path selection circuit. The memory cell array includes a plurality of bank arrays. The control logic circuit controls access to the memory cell array and generates a density mode signal based on a command. The first path selection circuit selectively provides write data to the error correction circuit.
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12.发明申请公开(公告)号：US20180322008A1
公开(公告)日：2018-11-08
申请号：US16015534
申请日：2018-06-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hoi-Ju Chung , Sang-Uhn Cha , Ho-Young Song , Hyun-Joong Kim
CPC classification number: G06F11/1068 , G06F3/0619 , G06F3/064 , G06F3/0679 , G11C29/52 , G11C29/70 , G11C2029/0409 , G11C2029/0411
Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.
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13.发明授权公开(公告)号：US10037244B2
公开(公告)日：2018-07-31
申请号：US15238216
申请日：2016-08-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hoi-Ju Chung , Sang-Uhn Cha , Ho-Young Song , Hyun-Joong Kim
CPC classification number: G06F11/1068 , G06F3/0619 , G06F3/064 , G06F3/0679 , G11C29/52 , G11C29/70 , G11C2029/0409 , G11C2029/0411
Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.
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14.发明授权公开(公告)号：US09805827B2
公开(公告)日：2017-10-31
申请号：US14817212
申请日：2015-08-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jong-Pil Son , Chul-Woo Park , Hoi-Ju Chung , Sang-Uhn Cha , Seong-Jin Jang
IPC: G11C11/16 , G11C11/4096 , G11C29/42 , G11C29/44
CPC classification number: G11C29/4401 , G11C11/16 , G11C11/1673 , G11C11/1675 , G11C11/4096 , G11C29/42 , G11C2029/4402
Abstract: A semiconductor memory device includes a memory cell array and a test circuit. The test circuit reads data stream from the memory cell array, configured to, on comparing bits of each first unit in the data stream, compares corresponding bits in the first units as each second unit and outputs a fail information signal including pass/fail information on the data stream and additional information on the data stream, in a test mode of the semiconductor memory device.
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15.发明授权公开(公告)号：US11994948B2
公开(公告)日：2024-05-28
申请号：US18164349
申请日：2023-02-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hoi-Ju Chung , Sang-Uhn Cha , Ho-Young Song , Hyun-Joong Kim
CPC classification number: G06F11/1068 , G06F3/0619 , G06F3/064 , G06F3/0679 , G11C29/52 , G11C2029/0409 , G11C2029/0411 , G11C29/70
Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.
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Patent Agency Ranking
16.发明授权公开(公告)号：US10705908B2
公开(公告)日：2020-07-07
申请号：US16015534
申请日：2018-06-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hoi-Ju Chung , Sang-Uhn Cha , Ho-Young Song , Hyun-Joong Kim
Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.
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17.发明授权公开(公告)号：US10002045B2
公开(公告)日：2018-06-19
申请号：US15209043
申请日：2016-07-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hoi-Ju Chung , Sang-Uhn Cha
CPC classification number: G06F11/1068 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/1048 , G11C7/20 , G11C11/1675 , G11C11/4072 , G11C2029/0407
Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a memory cell array, an input/output (I/O) gating circuit and an error correction circuit. The memory cell array includes a plurality of memory cells. The I/O gating circuit, before performing a normal memory operation on the memory cell array by a first unit, performs a cell data initializing operation by writing initializing bits in the memory cell array by a second unit different from the first unit. The error correction circuit performs an error correction code (ECC) encoding and an ECC decoding on a target page of the memory cell array by the second unit, based on the initializing bits. Therefore, power consumption in performing write operation may be reduced.
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公开(公告)号：US09953725B2
公开(公告)日：2018-04-24
申请号：US15395213
申请日：2016-12-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ye-Sin Ryu , Sang-Uhn Cha , Hoi-Ju Chung , Seong-Jin Cho
IPC: G11C29/44 , G11C29/56 , G11B20/18 , G01R31/3187 , G06F11/27 , G06F11/10 , G11C29/52 , G11C5/04 , G11C11/40 , G11C17/16 , G11C17/18 , G11C29/02 , G11C29/00
CPC classification number: G11C29/44 , G01R31/3187 , G06F11/1068 , G06F11/27 , G11B20/1816 , G11C5/04 , G11C11/40 , G11C17/16 , G11C17/18 , G11C29/027 , G11C29/4401 , G11C29/52 , G11C29/56004 , G11C29/56008 , G11C29/785 , G11C29/787 , G11C2029/4402 , G11C2029/5606
Abstract: A method of operating a semiconductor memory device is provided. In a method of operating a semiconductor memory device including a memory cell array which includes a plurality of bank arrays, memory cells in a first region of the memory cell array are tested to detect one or more failed cells in the first region, a fail address corresponding to the detected one or more failed cells is determined and the determined fail address is stored in a second region different from the first region, in the memory cell array.
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公开(公告)号：US20170110206A1
公开(公告)日：2017-04-20
申请号：US15395213
申请日：2016-12-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ye-Sin Ryu , Sang-Uhn Cha , Hoi-Ju Chung , Seong-Jin Cho
CPC classification number: G11C29/44 , G01R31/3187 , G06F11/1068 , G06F11/27 , G11B20/1816 , G11C5/04 , G11C11/40 , G11C17/16 , G11C17/18 , G11C29/027 , G11C29/4401 , G11C29/52 , G11C29/56004 , G11C29/56008 , G11C29/785 , G11C29/787 , G11C2029/4402 , G11C2029/5606
Abstract: A method of operating a semiconductor memory device is provided. In a method of operating a semiconductor memory device including a memory cell array which includes a plurality of bank arrays, memory cells in a first region of the memory cell array are tested to detect one or more failed cells in the first region, a fail address corresponding to the detected one or more failed cells is determined and the determined fail address is stored in a second region different from the first region, in the memory cell array.
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20.发明授权公开(公告)号：US11593199B2
公开(公告)日：2023-02-28
申请号：US17562505
申请日：2021-12-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hoi-Ju Chung , Sang-Uhn Cha , Ho-Young Song , Hyun-Joong Kim
Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.
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