公开(公告)号：US20230260923A1

公开(公告)日：2023-08-17

申请号：US18307277

申请日：2023-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il CHOI ,  Gyuho Kang ,  Un-Byoung Kang ,  Byeongchan Kim ,  Junyoung Park ,  Jongho Lee ,  Hyunsu Hwang

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L23/49822 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/16 ,  H01L23/3128 ,  H01L25/105 ,  H01L23/5383 ,  H01L2224/16225

Abstract: A semiconductor package including a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer may be provided. Each of the redistribution patterns may include a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion. The via portion, the pad portion, and the line portion may be connected to each other to form a single object. A level of a bottom surface of the pad portion may be lower than a level of a bottom surface of the line portion. A width of the line portion may have a largest value at a level between a top surface of the line portion and the bottom surface of the line portion.

公开(公告)号：US11682630B2

公开(公告)日：2023-06-20

申请号：US17349174

申请日：2021-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il Choi ,  Gyuho Kang ,  Un-Byoung Kang ,  Byeongchan Kim ,  Junyoung Park ,  Jongho Lee ,  Hyunsu Hwang

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5383 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/16225

Abstract: A semiconductor package including a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer may be provided. Each of the redistribution patterns may include a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion. The via portion, the pad portion, and the line portion may be connected to each other to form a single object. A level of a bottom surface of the pad portion may be lower than a level of a bottom surface of the line portion. A width of the line portion may have a largest value at a level between a top surface of the line portion and the bottom surface of the line portion.

公开(公告)号：US20240237349A1

公开(公告)日：2024-07-11

申请号：US18464348

申请日：2023-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsu Hwang ,  Un-Byoung Kang ,  Jumyong Park ,  Dongjoon Oh ,  Hyunchul Jung ,  Sanghoo Cho

IPC: H10B43/27 ,  G11C16/04 ,  H01L23/528 ,  H01L25/065 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

CPC classification number: H10B43/27 ,  G11C16/0483 ,  H01L23/5283 ,  H01L25/0652 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00 ,  H01L2225/06506

Abstract: A three-dimensional semiconductor memory device may include a bottom structure and a top structure thereon. The bottom structure may include a semiconductor substrate including a cell array region and a connection region extending therefrom, and a first stack including first gate electrodes and first interlayer insulating layers alternately stacked on the semiconductor substrate. The top structure may include a second stack including second gate electrodes and second interlayer insulating layers alternately stacked on the first stack. Respective lengths of the first gate electrodes in a second direction may decrease as a distance in a first direction increases, and respective lengths of the second gate electrodes in the second direction may increase as a distance in the first direction increases. The first direction may be perpendicular to a bottom surface of the semiconductor substrate, and the second direction may be parallel to the bottom surface of the semiconductor substrate.

公开(公告)号：US12027482B2

公开(公告)日：2024-07-02

申请号：US17568355

申请日：2022-01-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonggi Jin ,  Gyuho Kang ,  Unbyoung Kang ,  Heewon Kim ,  Jumyong Park ,  Hyunsu Hwang

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L24/08 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/53238 ,  H01L24/05 ,  H01L2224/02251 ,  H01L2224/05009 ,  H01L2224/05555 ,  H01L2224/05647 ,  H01L2224/08146

Abstract: A semiconductor chip includes: a semiconductor substrate; a pad insulating layer on the semiconductor substrate; a through electrode which penetrates the semiconductor substrate and the pad insulating layer and includes a conductive plug and a conductive barrier layer surrounding a sidewall of the conductive plug; and a bonding pad which surrounds a sidewall of the through electrode and is spaced apart from the conductive plug with the conductive barrier layer disposed therebetween.

公开(公告)号：US20240162104A1

公开(公告)日：2024-05-16

申请号：US18462010

申请日：2023-09-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsu Hwang ,  Jumyong Park ,  Solji Song ,  Dongjoon Oh ,  Hyunchul Jung ,  Sanghoo Cho

IPC: H01L23/31 ,  H01L21/78 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L23/3107 ,  H01L21/78 ,  H01L23/5226 ,  H01L24/08 ,  H01L2224/08145

Abstract: A semiconductor device may include a substrate, one or more front pads disposed on a front surface of the substrate, and a circuit layer including an insulating layer and at least one interconnection electrically connected to the one or more front pads. In some embodiments, the circuit layer may be disposed between the one or more front pads and the substrate. In some embodiments, a side surface of the circuit layer may include a burr that protrudes a height that is below a level of a front surface of the circuit layer. Additionally or alternatively, the burr may form a step portion in the circuit layer.

公开(公告)号：US11923309B2

公开(公告)日：2024-03-05

申请号：US17210044

申请日：2021-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsu Hwang ,  Junyun Kweon ,  Jumyong Park ,  Jin Ho An ,  Dongjoon Oh ,  Chungsun Lee ,  Ju-Il Choi

IPC: H01L23/538 ,  H01L21/48 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/5383 ,  H01L21/4857 ,  H01L23/5386 ,  H01L25/0652 ,  H01L25/105 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package includes a redistribution substrate including redistribution line patterns in a dielectric layer, and a semiconductor chip on the redistribution substrate. The semiconductor chip includes chip pads electrically connected to the redistribution line patterns. Each of the redistribution line patterns has a substantially planar top surface and a nonplanar bottom surface. Each of the redistribution line patterns includes a central portion and edge portions on opposite sides of the central portion. Each of the redistribution line patterns has a first thickness as a minimum thickness at the central portion and a second thickness as a maximum thickness at the edge portions.

公开(公告)号：US20230420397A1

公开(公告)日：2023-12-28

申请号：US18322570

申请日：2023-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsu Hwang ,  Unbyoung Kang ,  Jumyong Park ,  Solji Song ,  Dongjoon Oh ,  Hyunchul Jung

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L24/05 ,  H01L23/48 ,  H01L25/0657 ,  H01L24/16 ,  H01L2224/16145 ,  H01L2224/05082 ,  H01L2224/05561 ,  H01L2224/05567 ,  H01L2224/05025

Abstract: A includes a semiconductor substrate, a pad insulating layer disposed on the semiconductor substrate, a through electrode structure that partially penetrates the semiconductor substrate but does not penetrate the pad insulating layer, an insulating liner that at least partially surrounds the through electrode structure, an insulating sidewall that penetrates the pad insulating layer, a part of the semiconductor substrate and at least a part of the insulating liner, and includes a pad hole formed therein, and a bonding pad structure disposed on the pad insulating layer and that fills the pad hole, and contacts the through electrode structure

公开(公告)号：US11854893B2

公开(公告)日：2023-12-26

申请号：US17850714

申请日：2022-06-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junyun Kweon ,  Jumyong Park ,  Solji Song ,  Dongjoon Oh ,  Chungsun Lee ,  Hyunsu Hwang

IPC: H01L21/78 ,  H01L21/02 ,  H01L23/00

CPC classification number: H01L21/78 ,  H01L21/0206 ,  H01L24/80 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/94 ,  H01L2224/97

Abstract: A method of manufacturing a semiconductor package, includes forming a mask layer on a wafer, the wafer including a semiconductor substrate and an insulating layer; forming a groove in the semiconductor substrate by performing a first laser grooving process; expanding an opening of the mask layer opened by the first laser grooving process by performing a second laser grooving process; exposing a portion of the insulating layer by removing a portion of the mask layer; and cutting the semiconductor substrate while removing the portion of the insulating layer exposed during the exposing by performing a dicing process.

公开(公告)号：US20220037255A1

公开(公告)日：2022-02-03

申请号：US17210044

申请日：2021-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsu Hwang ,  Junyun Kweon ,  Jumyong Park ,  Jin Ho An ,  Dongjoon Oh ,  Chungsun Lee ,  Ju-il Choi

IPC: H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H01L21/48

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package includes a redistribution substrate including redistribution line patterns in a dielectric layer, and a semiconductor chip on the redistribution substrate. The semiconductor chip includes chip pads electrically connected to the redistribution line patterns. Each of the redistribution line patterns has a substantially planar top surface and a nonplanar bottom surface. Each of the redistribution line patterns includes a central portion and edge portions on opposite sides of the central portion. Each of the redistribution line patterns has a first thickness as a minimum thickness at the central portion and a second thickness as a maximum thickness at the edge portions.