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公开(公告)号：US20220222138A1
公开(公告)日：2022-07-14
申请号：US17397321
申请日：2021-08-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sehwan PARK , Jinyoung Kim , Ilhan Park , Youngdeok Seo
Abstract: A memory device may determine cell count information from a threshold voltage distribution of memory cells and may determine a detection case based on the cell count information when an error in read data, received from the memory device performing a read operation is not corrected. A memory controller may control the memory device to execute a read operation using a development time determined in consideration of an offset voltage of a read voltage corresponding to the detection case. When an error in the read data is successfully corrected, the memory controller may update a table, stored in the memory controller, using a dynamic offset voltage obtained by inputting the cell count information to a machine learning model.
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公开(公告)号：US11817153B2
公开(公告)日：2023-11-14
申请号：US17503197
申请日：2021-10-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jinyoung Kim , Sehwan Park , Ilhan Park , Youngdeok Seo , Dongmin Shin
CPC classification number: G11C16/16 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/26
Abstract: A memory device may include a memory block and a control circuit. The memory block may include a first sub-block and a second sub-block that are connected between a common source line and a plurality of bit lines and may be vertically stacked. The control circuit may be configured to select any one of the common source line and the plurality of bit lines as a transmission path of an erase voltage based on positions of the first sub-block and the second sub-block, and perform erase operations on the first sub-block and the second sub-block in units of sub-blocks.
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公开(公告)号：US20230154542A1
公开(公告)日：2023-05-18
申请号：US17984890
申请日：2022-11-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jungmin Park , Minseok Kim , Junyong Park , Suyong Kim , Ilhan Park
Abstract: A non-volatile memory device includes a plurality of cell strings in a vertical direction, each of the plurality of cell strings including a plurality of memory cells respectively connected to a plurality of word lines, and an erase control transistor having a first end connected to at least one of both ends of plurality of memory cells and a second end connected to at least one of both ends of each of the plurality of cell strings, and a row decoder configured to apply a first bias voltage to the plurality of word lines in a first period in which an erase voltage applied to the second end of the erase control transistor increases to a target level and to apply a second bias voltage higher than the first bias voltage to at least some of the plurality of word lines in a second period after the first period.
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公开(公告)号：US11610639B2
公开(公告)日：2023-03-21
申请号：US17336378
申请日：2021-06-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Eunhyang Park , Jinyoung Kim , Jisang Lee , Sehwan Park , Ilhan Park
Abstract: A reading method for a non-volatile memory device, includes performing a normal read operation using a default read level in response to a first read command; and performing a read operation using a multiple on-chip valley search (OVS) sensing operation in response to a second read command, when read data read in the normal read operation are uncorrectable.
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公开(公告)号：US11475972B2
公开(公告)日：2022-10-18
申请号：US17368460
申请日：2021-07-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Younghwi Yang , Ilhan Park , Jinyoung Kim , Sehwan Park , Dongmin Shin
Abstract: A controller includes control pins, a buffer memory, an error correction circuit, and a processor driving a read level search unit for a read operation of at least one non-volatile memory device, in which the read level search unit receives fail bit information of a sector error-corrected in the first page from the at least one non-volatile memory device when the error correction of the first read data is not possible, and searches for an optimal read level or set a soft decision offset using the fail bit information.
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Patent Agency Ranking
公开(公告)号：US11386974B2
公开(公告)日：2022-07-12
申请号：US17147851
申请日：2021-01-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sehwan Park , Jinyoung Kim , Ilhan Park , Kyoman Kang , Sangwan Nam
Abstract: A non-volatile memory device includes a memory cell array including a plurality of memory blocks that includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to select one among the plurality of memory blocks, based on an address, a voltage generator configured to apply word line voltages corresponding to selected word lines and unselected word lines, among the plurality of word lines, page buffers connected to the plurality of bit lines and configured to read data from a memory cell connected to one among the selected word lines of the selected one among the plurality of memory blocks, and a control logic configured to control the row decoder, the voltage generator, and the page buffers.
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公开(公告)号：US11372551B2
公开(公告)日：2022-06-28
申请号：US16898935
申请日：2020-06-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Byungyong Choi , Doohyun Kim , Changkyu Seol , Ilhan Park
Abstract: A method of operating a memory controller, the method including performing a state shaping operation on received data based on state shaping information in response to a write request, the received data and the write request being received from a host, the state shaping information representing a memory cell characteristic corresponding to a memory cell group on which the received data is to be programmed, and the state shaping information being received from a memory device, and transmitting transformation data to the memory device, the transformation data being generated through the state shaping operation.
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公开(公告)号：US12002518B2
公开(公告)日：2024-06-04
申请号：US17710283
申请日：2022-03-31
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yongsung Cho , Kyoman Kang , Minhwi Kim , Ilhan Park , Jinyoung Chun
CPC classification number: G11C16/24 , G11C16/0483 , G11C16/26
Abstract: A memory device is provided. The memory device includes: a memory cell array including a plurality of memory cells; a page buffer circuit connected to the memory cell array through a plurality of bit lines and including a page buffer connected to each of the plurality of bit lines, the page buffer including at least one first latch for storing data based on a voltage level of a first sensing node; and a control circuit configured to adjust a level of a voltage signal provided to the page buffer circuit. The page buffer includes a trip control transistor arranged between the at least one first latch and the first sensing node, and wherein the control circuit is further configured to, based on a read operation being performed on the memory cell array, control a trip control voltage to be provided to a gate of the trip control transistor. A level of the trip control voltage varies according to a temperature of the memory device.
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公开(公告)号：US11915770B2
公开(公告)日：2024-02-27
申请号：US17736395
申请日：2022-05-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Minseok Kim , Junyong Park , Doohyun Kim , Ilhan Park
IPC: G11C16/34 , G11C11/56 , G11C16/04 , G11C16/10 , H01L25/065 , H01L25/18 , H01L23/00 , G11C29/10 , G11C16/16
CPC classification number: G11C16/3495 , G11C11/5628 , G11C11/5635 , G11C11/5671 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C29/10 , H01L24/08 , H01L25/0657 , H01L25/18 , H01L2224/08145 , H01L2924/1431 , H01L2924/14511
Abstract: In a method of reducing reliability degradation of a nonvolatile memory device, the nonvolatile memory device in which initial data having an initial threshold voltage distribution is stored in a plurality of memory cells connected to a plurality of wordlines is provided. Before a first process causing reliability degradation is performed, a first write operation is performed such that first data having a first threshold voltage distribution is stored into memory cells connected to first wordlines. The first wordlines have a degree of reliability degradation less than a reference value. Before the first process is performed, a second write operation is performed such that second data having a second threshold voltage distribution is stored into memory cells connected to second wordlines. The second wordlines have a degree of reliability degradation greater than or equal to the reference value.
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公开(公告)号：US11869599B2
公开(公告)日：2024-01-09
申请号：US18064635
申请日：2022-12-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jungmin Park , Kyunghoon Sung , Ilhan Park , Jisang Lee , Joon Suc Jang , Sanghyun Joo
CPC classification number: G11C16/24 , G11C16/0483 , G11C16/10 , H01L24/00 , H01L25/0657 , H01L25/18 , H01L2224/08145 , H01L2924/1431 , H01L2924/14511
Abstract: A nonvolatile memory device includes cell strings commonly connected between bitlines and a source line where the cell strings are grouped into memory blocks. During a precharge period, channels of the cell strings of a selected memory block are precharged by applying a gate induced drain leakage (GIDL) on voltage to gates of GIDL transistors included in the cell strings of the selected memory block where the GIDL on voltage has a voltage level to induce GIDL. During the precharge period, precharge of channels of the cell strings of an unselected memory block are prevented by controlling a gate voltage of GIDL transistors included in the cell strings of the unselected memory block to prevent the GIDL. During a program execution period after the precharge period, memory cells of the selected memory block connected to a selected wordline are programmed by applying a program voltage to the selected wordline.
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