公开(公告)号：US09378815B2

公开(公告)日：2016-06-28

申请号：US14878629

申请日：2015-10-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Kyu Lee ,  Dae-Won Kim

IPC: G11C11/00 ,  G11C7/00 ,  G11C13/00 ,  G11C11/16

CPC classification number: G11C13/004 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1677 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2213/76 ,  G11C2213/79

Abstract: A resistive memory device includes a memory cell array having a plurality of memory cells therein, which operate in response to word line driving and column selecting signals. Each of memory cells includes a resistive device and a cell transistor connected in series. An I/O sense amplifier senses and amplifies data output from the memory cell array to thereby generate output data, and also generate program current based on input data and provide the program current to the memory cell array. The resistive memory device is also configured to read output data from the I/O sense amplifier and adjust interface states of the cell transistors based on a voltage level of the output data during a test mode.

Abstract translation: 电阻式存储器件包括其中具有多个存储单元的存储单元阵列，其响应于字线驱动和列选择信号而工作。 每个存储单元包括串联连接的电阻器件和单元晶体管。 I / O读出放大器感测并放大从存储单元阵列输出的数据，从而生成输出数据，并且还根据输入数据生成程序电流，并将程序电流提供给存储单元阵列。 电阻性存储器件还被配置为从I / O读出放大器读取输出数据，并且在测试模式期间基于输出数据的电压电平来调节单元晶体管的接口状态。

公开(公告)号：US08928341B2

公开(公告)日：2015-01-06

申请号：US13737286

申请日：2013-01-09

Applicant: Samsung Electronics Co. Ltd.

Inventor： Han-Awl Lee ,  Jae-Kyu Lee ,  Woong-Hae Choi ,  Byoung-Hee Lee

IPC: G01R31/00 ,  G01R31/319

CPC classification number: G01R31/31924 ,  G01R31/001 ,  G01R31/002 ,  H04M1/24

Abstract: An apparatus and a method for automated testing of electrostatic discharge of a Device Under Test (DUT) are provided. In the apparatus and the method, an electrostatic pulse is applied to the DUT, a malfunction type is detected from the DUT, and a control command is transmitted to the DUT to return a test mode of the DUT to a normal mode according to the detected malfunction type.

Abstract translation: 提供了一种用于自动测试被测设备（DUT）的静电放电的设备和方法。 在该装置和方法中，向DUT施加静电脉冲，从DUT检测到故障类型，并且向DUT发送控制命令，以根据检测到的DUT将测试模式返回到正常模式 故障类型。

公开(公告)号：US12176362B2

公开(公告)日：2024-12-24

申请号：US17856022

申请日：2022-07-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-Woong Seo ,  Jungchak Ahn ,  Jae-Kyu Lee

IPC: H01L27/146 ,  H04N25/59 ,  H04N25/60 ,  H04N25/772 ,  H10B12/00

Abstract: An image sensor device includes a digital pixel that includes a photo detector, a comparator, and a memory circuit, a pixel driver that controls the digital pixel, and a digital logic circuit that performs a digital signal processing operation on a digital signal output from the digital pixel. The photo detector and a first portion of the comparator are formed in a first semiconductor die, a second portion of the comparator, the memory circuit, and the pixel driver are formed in a second semiconductor die under the first semiconductor die, and the digital logic circuit is formed in a third semiconductor die under the second semiconductor die.

公开(公告)号：US11482285B2

公开(公告)日：2022-10-25

申请号：US16936917

申请日：2020-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-woo Kim ,  Jae-Kyu Lee ,  Ki-seok Suh ,  Hyeong-sun Hong ,  Yoo-sang Hwang ,  Gwan-hyeob Koh

IPC: H01L23/528 ,  H01L43/12 ,  G11C14/00 ,  H01L45/00 ,  H01L29/08 ,  H01L27/108 ,  H01L29/423 ,  H01L43/08 ,  H01L43/02 ,  H01L27/24 ,  H01L27/22 ,  H01L27/105 ,  H01L27/02 ,  G11C7/10 ,  G11C11/00

Abstract: An integrated circuit (IC) device may include a single substrate that includes a single chip, and a plurality of memory cells spaced apart from one another on the substrate and having different structures. Manufacturing the IC device may include forming a plurality of first word lines in a first region of the substrate, and forming a plurality of second word lines in or on a second region of the substrate. Capacitors may be formed on the first word lines. Source lines may be formed on the second word lines. An insulation layer that covers the plurality of capacitors and the plurality of source lines may be formed in the first region and the second region. A variable resistance structure may be formed at a location spaced apart from an upper surface of the substrate by a first vertical distance, in the second region.

公开(公告)号：US10141373B2

公开(公告)日：2018-11-27

申请号：US15387751

申请日：2016-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Song-Yi Kim ,  Jae-Kyu Lee ,  Dae-Hwan Kang ,  Gwan-Hyeob Koh

IPC: H01L27/24 ,  H01L45/00

Abstract: A plurality of first conductive patterns is disposed on a substrate. Each of the plurality of first conductive patterns extends in a first direction. A first selection pattern is disposed on each of the plurality of first conductive patterns. A first barrier portion surrounds the first selection pattern. A first electrode and a first variable resistance pattern are disposed on the first selection pattern. A plurality of second conductive patterns is disposed on the first variable resistance pattern. Each of the plurality of second conductive patterns extends in a second direction crossing the first direction.

公开(公告)号：US20180249405A1

公开(公告)日：2018-08-30

申请号：US15890903

申请日：2018-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Prasad Basavaraj DANDRA ,  Vijay Ganesh Surisetty ,  Siddhi Chandrashekhar Mayekar ,  Akshay Rastogi ,  Jae-Kyu Lee

IPC: H04W48/18 ,  H04W48/16 ,  H04W8/22

CPC classification number: H04W48/18 ,  H04W8/22 ,  H04W48/16 ,  H04W88/06

Abstract: Some example embodiments disclose methods for selecting registered public land mobile network (RPLMN) radio access technology (RAT) modes in wireless communication devices. The method as disclosed herein includes determining location information of the wireless communication device; validating the location information; deriving a RPLMN from the validated location information when the validating is successful; storing a RPLMN access technology (AccTech) based on the derived RPLMN; and selecting a RAT mode using the stored RPLMN AccTech.

公开(公告)号：US10008539B2

公开(公告)日：2018-06-26

申请号：US15234257

申请日：2016-08-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Kyu Lee ,  Sung-In Kim ,  Ki-Seok Suh

IPC: H01L27/22 ,  G11C11/16

CPC classification number: H01L27/228 ,  G11C11/1655 ,  G11C11/1659

Abstract: A magnetoresistive random access memory (MRAM) device including a substrate including a plurality of active patterns arranged along a first direction, each of the active patterns extending in a diagonal direction with respect to the first direction; a plurality of gate structures on the substrate, the gate structures extending in a second direction substantially perpendicular to the first direction; a source line structure electrically connected to source regions of the respective active patterns, the source line structure extending in the first direction; a plurality of magnetic tunnel junction (MTJ) structures electrically connected to drain regions of the respective active patterns, the MTJ structures being spaced apart from each other; and a bit line structure electrically connected to the MTJ structures in respective memory cells, the memory cells sharing with the source line structure.

公开(公告)号：US09768053B2

公开(公告)日：2017-09-19

申请号：US14955193

申请日：2015-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Won Kim ,  Jae-Kyu Lee

IPC: H01L27/24 ,  H01L45/00 ,  H01L21/762 ,  H01L21/308 ,  H01L27/108

CPC classification number: H01L21/762 ,  H01L21/3083 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/2436 ,  H01L27/2463 ,  H01L29/4236 ,  H01L29/78 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

Abstract: A method of forming patterns of a semiconductor device, including partially etching an upper portion of a substrate to form first preliminary active patterns and a first trench, each of the first preliminary active patterns having a first width, and the first trench having a second width of about 2 to 3 times the first width; forming an insulating spacer on each sidewall of the first trench to form a second trench having the first width; forming a second preliminary active pattern in the second trench, the second preliminary active pattern having the first width; partially etching the first and second preliminary active patterns to form a plurality of first active patterns and a plurality of second active patterns and an opening between the plurality of first and second active patterns; and forming an insulation pattern to fill the opening.