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公开(公告)号：US20240249782A1
公开(公告)日：2024-07-25
申请号：US18423047
申请日：2024-01-25
发明人： Minkyeong CHOI , Joonsuc Jang , Ji-Sang Lee
CPC分类号： G11C16/349 , G11C16/0483
摘要： A memory system includes: a memory device including a memory cell array and a control circuit; and a temperature sensor configured to measure a temperature of the memory device to generate a temperature value, wherein the control circuit is configured to: set a compensation sensing parameter based on the temperature value, determine a sensing parameter by applying the compensation sensing parameter to a basic sensing parameter corresponding to a read mode among a plurality of read modes having different read speeds, and read data from the memory cell array based on the sensing parameter.
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12.发明授权公开(公告)号：US12040020B2
公开(公告)日：2024-07-16
申请号：US17854163
申请日：2022-06-30
发明人： Kwangho Choi , Minseok Kim , Il Han Park , Jun-Yong Park , Joonsuc Jang
CPC分类号： G11C16/0433 , G11C16/08 , G11C16/12 , G11C16/26
摘要： Disclosed is a memory device which includes a history table and communicates with a storage controller. A method of operating the memory device includes receiving a first request indicating a first core operation of a first memory block from the storage controller, determining whether history data of the first memory block have a first value or a second value, with reference to the history table, in response to the first request, when it is determined that the history data of the first memory block have the first value, performing the first core operation corresponding to a first type on the first memory block, and after performing the first core operation corresponding to the first type on the first memory block, updating the history data of the first memory block in the history table from the first value to the second value.
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13.发明授权公开(公告)号：US11915763B2
公开(公告)日：2024-02-27
申请号：US17698056
申请日：2022-03-18
发明人： Joonsuc Jang
IPC分类号： H04L1/00 , G06F11/00 , G06F11/30 , G08C25/00 , H03M13/00 , G11C16/10 , G06F3/06 , G06F11/10 , G11C11/56 , G11C16/08 , G11C16/26 , G11C16/34 , G11C16/04
CPC分类号： G11C16/10 , G06F3/0604 , G06F3/0619 , G06F3/0644 , G06F3/0647 , G06F3/0659 , G06F3/0679 , G06F11/1068 , G11C11/56 , G11C16/08 , G11C16/26 , G11C16/3459 , G11C16/0483
摘要： An operating method of a memory system includes preprogramming multi-page data of a memory controller to a nonvolatile memory device, generating a state group code based on multi-bit data of the multi-page data, and each state group data of the state group code having less number of bits than corresponding multi-bit data, detecting sudden power-off occurring after the preprogramming, backing up, in response to the detecting of the sudden power-off occurring, the state group code to the nonvolatile memory device, recovering, after power is recovered from the sudden power-off, the multi-page data from the nonvolatile memory device, based on the state group code, reprogramming the multi-page data to the nonvolatile memory device, and reprogramming, in response to the detecting of the sudden power-off not occurring, the multi-page data of the memory controller to the nonvolatile memory device.
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14.发明授权公开(公告)号：US11823753B2
公开(公告)日：2023-11-21
申请号：US18128596
申请日：2023-03-30
发明人： Joonsuc Jang , Hyunggon Kim , Sangbum Yun , Dongwook Kim , Kyungsoo Park , Sejin Baek
CPC分类号： G11C16/3459 , G11C7/106 , G11C7/1045 , G11C7/1048 , G11C7/1087 , G11C16/10 , G11C16/24 , G11C16/26 , G11C16/30
摘要： A method of programming a nonvolatile memory device includes performing a single-pulse program operation in a program loop, determining whether a condition is satisfied in the a program loop, and performing a multi-pulse program operation in a next program loop when the condition is satisfied. The single-pulse program operation includes applying a first program pulse and applying plural verification pulses, the multi-pulse program operation includes applying a second program pulse, applying a third program pulse, and applying plural verification pulses, and each of the second program pulse and the third program pulse has a level lower than a level of the first program pulse.
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公开(公告)号：US11562804B2
公开(公告)日：2023-01-24
申请号：US17469422
申请日：2021-09-08
发明人： Sehwan Park , Jinyoung Kim , Youngdeok Seo , Dongmin Shin , Joonsuc Jang , Sungmin Joe
摘要： A storage device includes a nonvolatile memory device and a memory controller to control the nonvolatile memory device. The nonvolatile memory device includes a memory cell array. The memory cell array includes a normal cell region, a parity cell region and a redundancy cell region. First bit-lines are connected to the normal cell region and the parity cell region and second bit-lines are connected to the redundancy cell region. The memory controller includes an error correction code (ECC) engine to generate parity data. The memory controller stores user data in the normal cell region, controls the nonvolatile memory device to perform a column repair on first defective bit-lines among the first bit-lines, assigns additional column addresses to the first defective bit-lines and the second bit-lines and stores at least a portion of the parity data in a region corresponding to the additionally assigned column addresses.
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公开(公告)号：US11562794B2
公开(公告)日：2023-01-24
申请号：US17324333
申请日：2021-05-19
发明人： Jisu Kim , Hyunggon Kim , Sangsoo Park , Joonsuc Jang , Minseok Kim
IPC分类号： G06F11/10 , G06F11/07 , G06F11/30 , G06F11/14 , G11C16/26 , G11C11/56 , G11C16/04 , G11C16/24 , H01L23/00 , H01L25/065 , H01L25/18
摘要： Provided is a storage device that performs a read operation by using a time interleaved sampling page buffer. The storage device controls a sensing point in time, when bit lines of even page buffer circuits are sensed, and a sensing point in time, when bit lines of odd page buffer circuits are sensed, with a certain time difference, and performs an Even Odd Sensing (EOS) operation in a stated order of even sensing and odd sensing. The storage device performs a two-step EOS operation and performs a main sensing operation on a selected memory cell according to a result of the two-step EOS operation.
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公开(公告)号：US11450386B2
公开(公告)日：2022-09-20
申请号：US17221833
申请日：2021-04-04
发明人： Sungmin Joe , Sangsoo Park , Joonsuc Jang , Kihoon Kang , Yonghyuk Choi
摘要： A nonvolatile memory device that performs two-way channel precharge during programming is provided. A program operation of the nonvolatile memory device simultaneously performs a first precharge operation in a bit line direction and a second precharge operation in a source line direction on channels of a plurality of cell strings before programming a selected memory cell to initialize the channels. The first precharge operation precharges the channels of the plurality of cell strings using a first precharge voltage applied to the bit line through first and second string selection transistors, and the second precharge operation precharges the channels of the plurality of cell strings using a second precharge voltage applied to the source line through first and second ground selection transistors.
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18.发明申请公开(公告)号：US20220208271A1
公开(公告)日：2022-06-30
申请号：US17698056
申请日：2022-03-18
发明人： Joonsuc Jang
摘要： An operating method of a memory system includes preprogramming multi-page data of a memory controller to a nonvolatile memory device, generating a state group code based on multi-bit data of the multi-page data, and each state group data of the state group code having less number of bits than corresponding multi-bit data, detecting sudden power-off occurring after the preprogramming, backing up, in response to the detecting of the sudden power-off occurring, the state group code to the nonvolatile memory device, recovering, after power is recovered from the sudden power-off, the multi-page data from the nonvolatile memory device, based on the state group code, reprogramming the multi-page data to the nonvolatile memory device, and reprogramming, in response to the detecting of the sudden power-off not occurring, the multi-page data of the memory controller to the nonvolatile memory device.
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