公开(公告)号：US10790278B2

公开(公告)日：2020-09-29

申请号：US16275761

申请日：2019-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mingyu Kim ,  Kang-Ill Seo

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/308 ,  H01L29/78

Abstract: A semiconductor device including a semiconductor substrate having a recessed top portion and a non-recessed top portion, a first fin protruding upward from a non-recessed top portion with a first thickness, a second fin protruding upward from the recessed top portion with a second thickness greater than the first thickness, a first gate structure on the non-recessed top portion and surrounding the first fin to a first height from the non-recessed top portion, and a second gate structure on the recessed top portion and surrounding the second fin to a second height different from the first height from the recessed top portion may be provided.

公开(公告)号：US09991259B2

公开(公告)日：2018-06-05

申请号：US15387022

申请日：2016-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Jae Kang ,  Jin-Wook Lee ,  Kang-Ill Seo ,  Yong-Min Cho

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/027 ,  H01L21/768 ,  H01L23/522 ,  H01L27/02 ,  H01L23/528 ,  H01L23/532 ,  G03F7/20

CPC classification number: H01L27/0886 ,  G03F7/70 ,  H01L21/0274 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53271 ,  H01L27/0207

Abstract: Provided are a semiconductor device and a fabricating method thereof. The fabricating method includes forming first to fourth fins, each extending in a first direction, to be spaced apart in a second direction intersecting the first direction, forming first and second gate lines, each extending in the second direction, on the first to fourth fins to be spaced apart in the first direction, forming a first contact on the first gate line between the first and second fins, forming a second contact on the first gate line between the third and fourth fins, forming a third contact on the second gate line between the first and second fins, forming a fourth contact on the second gate line between the third and fourth fins and forming a fifth contact on the first to fourth contacts so as to overlap with the second contact and the third contact and so as not to overlap with the first contact and the fourth contact, wherein the fifth contact is arranged to diagonally traverse a quadrangle defined by the first to fourth contacts.

公开(公告)号：US09818748B2

公开(公告)日：2017-11-14

申请号：US15440541

申请日：2017-02-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Dae Suk ,  Kang-Ill Seo

IPC: H01L21/00 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/845 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

Abstract: A semiconductor device is provided. A substrate includes a first region and a second region. A first wire pattern, extending in a first direction, is formed at a first height from the substrate of the first region. A second wire pattern, extending in a second direction, is formed at a second height from the substrate of the second region. The first height is different from the second height. A first gate electrode, surrounding the first wire pattern, extends in a third direction crossing the first direction. A second gate electrode, surrounding the second wire pattern, extends in a fourth direction crossing the second direction. A first gate insulation layer is formed along a circumference of the first wire pattern and a sidewall of the first gate electrode. A second gate insulation layer is formed along a circumference of the second wire pattern and a sidewall of the second gate electrode.

公开(公告)号：US09653462B2

公开(公告)日：2017-05-16

申请号：US14583252

申请日：2014-12-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Dae Suk ,  Kang-Ill Seo

IPC: H01L21/336 ,  H01L27/088 ,  H01L29/66 ,  H01L21/225 ,  H01L29/78 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L27/0886 ,  H01L21/225 ,  H01L21/76805 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/485 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device includes a fin type active pattern extended in a first direction and disposed on a substrate. A first gate electrode and a second gate electrode are disposed on the fin type active pattern. The first gate electrode and the second gate electrode are extended in a second direction crossing the first direction. A trench region is disposed in the fin type active pattern and between the first gate electrode and the second gate electrode. A source/drain region is disposed on a surface of the trench region. A source/drain contact is disposed on the source/drain region. The source/drain contact includes a first insulating layer disposed on the source/drain region and a metal oxide layer disposed on the first insulating layer.

公开(公告)号：US09418896B2

公开(公告)日：2016-08-16

申请号：US14539579

申请日：2014-11-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Jae Kang ,  Jin-Wook Lee ,  Kang-Ill Seo ,  Yong-Min Cho

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/3213

CPC classification number: H01L27/0886 ,  G03F7/70 ,  H01L21/0274 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53271 ,  H01L27/0207

Abstract: Provided are a semiconductor device and a fabricating method thereof. The fabricating method includes forming first to fourth fins, each extending in a first direction, to be spaced apart in a second direction intersecting the first direction, forming first and second gate lines, each extending in the second direction, on the first to fourth fins to be spaced apart in the first direction, forming a first contact on the first gate line between the first and second fins, forming a second contact on the first gate line between the third and fourth fins, forming a third contact on the second gate line between the first and second fins, forming a fourth contact on the second gate line between the third and fourth fins and forming a fifth contact on the first to fourth contacts so as to overlap with the second contact and the third contact and so as not to overlap with the first contact and the fourth contact, wherein the fifth contact is arranged to diagonally traverse a quadrangle defined by the first to fourth contacts.

Abstract translation: 提供一种半导体器件及其制造方法。 制造方法包括：形成第一至第四鳍片，每个翼片沿第一方向延伸，沿与第一方向相交的第二方向间隔开，形成第一和第二栅极线，每个沿第二方向延伸，第一至第四鳍片 在所述第一方向上间隔开，在所述第一和第二鳍之间的所述第一栅极线上形成第一接触，在所述第三和第四鳍之间的所述第一栅极线上形成第二接触，在所述第二栅极线上形成第三接触 在第一和第二散热片之间，在第三和第四鳍之间的第二栅极线上形成第四触点，并在第一至第四触点上形成第五触点，以便与第二触点和第三触点重叠， 与第一触点和第四触点重叠，其中第五触点布置成对角地横过由第一至第四触点限定的四边形。

公开(公告)号：US09209179B2

公开(公告)日：2015-12-08

申请号：US14253439

申请日：2014-04-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Wook Lee ,  Kang-Ill Seo

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L29/0692 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/7856

Abstract: A semiconductor device is provided. A substrate includes first and second active fins disposed in a row along a first direction. The first and second active fins are spaced apart from each other. A first dummy gate and a second dummy gate are disposed on the substrate and are extended in a second direction intersecting the first direction. The first dummy gate covers an end portion of the first active fin. The second dummy gate covers an end portion of the second active fin facing the end portion of the first active fin. A first dummy spacer is disposed on a sidewall of the first dummy gate. A second dummy spacer is disposed on a sidewall of the second dummy gate. The sidewall of the second dummy gate faces the sidewall of the first dummy gate. The first dummy spacer is in contact with the second dummy spacer.

Abstract translation: 提供半导体器件。 衬底包括沿着第一方向排成一排的第一和第二活性鳍。 第一和第二活动翅片彼此间隔开。 第一伪栅极和第二伪栅极设置在基板上并沿与第一方向相交的第二方向延伸。 第一伪栅极覆盖第一有源鳍片的端部。 第二伪栅极覆盖面向第一有源鳍片的端部的第二有源鳍片的端部。 第一虚拟间隔物设置在第一伪栅极的侧壁上。 第二虚拟间隔物设置在第二虚拟栅极的侧壁上。 第二伪栅极的侧壁面向第一虚拟栅极的侧壁。 第一假间隔件与第二假间隔件接触。

公开(公告)号：US20250149340A1

公开(公告)日：2025-05-08

申请号：US18678183

申请日：2024-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungchan Yun ,  Kang-Ill Seo

IPC: H01L21/28 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: Transistor devices are provided. A transistor device includes a substrate and a transistor stack on the substrate. The transistor stack includes a lower transistor and an upper transistor that is on top of the lower transistor. Moreover, the transistor device includes a gate-cut on the substrate, adjacent the transistor stack. The gate-cut has a first sloped sidewall and a second sloped sidewall that is opposite the first sloped sidewall. Related methods of forming transistor devices are also provided.

公开(公告)号：US12230571B2

公开(公告)日：2025-02-18

申请号：US17576007

申请日：2022-01-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gilhwan Son ,  Hoonseok Seo ,  Saehan Park ,  Byounghak Hong ,  Kang-Ill Seo

IPC: H01L23/528 ,  H01L21/74 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/485 ,  H01L23/535 ,  H01L27/088

Abstract: Methods of forming an integrated circuit devices may include forming a transistor on a first surface of a substrate. The transistor may include an active region, a source/drain region contacting the active region and a gate electrode on the active region. The methods may also include forming a conductive wire that is electrically connected to the source/drain region, forming a trench extending through the substrate by etching a second surface of the substrate, which is opposite the first surface of the substrate, and forming a power rail in the trench. The power rail is electrically connected to conductive wire.

公开(公告)号：US20240355878A1

公开(公告)日：2024-10-24

申请号：US18456571

申请日：2023-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEUNG MIN SONG ,  Panjae Park ,  Kang-Ill Seo

IPC: H01L29/06 ,  H01L21/8234 ,  H01L25/07 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/823412 ,  H01L25/074 ,  H01L27/088 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: Integrated circuit devices may include an upper transistor structure on a substrate, the upper transistor structure comprising an upper channel region and an upper gate electrode on the upper channel region; a lower transistor structure between the substrate and the upper transistor structure, the lower transistor structure comprising a lower channel region and a lower gate electrode on the lower channel region; and an intergate contact between the lower gate electrode and the upper gate electrode. The lower gate electrode may be electrically connected to the upper gate electrode through the intergate contact, and a portion of a lower surface of the intergate contact may protrude beyond a side surface of the lower gate electrode.

公开(公告)号：US20240332131A1

公开(公告)日：2024-10-03

申请号：US18448482

申请日：2023-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： JINTAE KIM ,  Keumseok Park ,  Kang-Ill Seo

IPC: H01L23/48 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/0688 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: Integrated circuit devices may include a power switch cell including an upper transistor on a substrate and a lower transistor between the substrate and the upper transistor. The upper transistor may include an upper channel region, first and second upper source/drain regions, and an upper gate electrode on the upper channel region. The lower transistor may include a lower channel region, first and second lower source/drain regions, and a lower gate electrode on the lower channel region. The first and second upper source/drain regions and the first and second lower source/drain regions may have the same conductivity type, the first upper source/drain region and the first lower source/drain region may be electrically connected to each other, the second upper source/drain region and the second lower source/drain region may be electrically connected to each other, and the upper and lower gate electrodes may be electrically connected to each other.