公开(公告)号：US20240243172A1

公开(公告)日：2024-07-18

申请号：US18195150

申请日：2023-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaejik Baek ,  Seungchan Yun ,  Kang-ill Seo

IPC: H01L29/06 ,  H01L21/8238 ,  H01L25/07 ,  H01L27/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/823807 ,  H01L25/074 ,  H01L27/0688 ,  H01L27/092 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: Provided is a three-dimensionally-stacked field-effect transistor (3DSFET) device including a plurality of 3DSFETs on a single substrate, wherein each of the 3DSFET includes: a 1st channel structure surrounded by a 1st gate structure; and a 2nd channel structure surrounded by a 2nd gate structure, the 2nd channel structure provided on the 1st channel structure, and wherein, in at least one of the 3DSFETs, the 1st gate structure is isolated from the 2nd gate structure through a barrier layer including a dielectric material comprising tantalum.

公开(公告)号：US11482619B2

公开(公告)日：2022-10-25

申请号：US17026551

申请日：2020-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghwan Han ,  Seungchan Yun

IPC: H01L29/78 ,  H01L27/092 ,  H01L27/12 ,  H01L21/8238 ,  H01L29/08

Abstract: A semiconductor device includes a substrate including an active region that extends in a first direction; a gate structure that intersects the active region and that extends in a second direction; a source/drain region on the active region on at least one side of the gate structure; a contact plug on the source/drain region on the at least one side of the gate structure; and a contact insulating layer on sidewalls of the contact plug, wherein a lower end of the contact plug is closer to the substrate than a lower end of the source/drain region.

公开(公告)号：US12243946B2

公开(公告)日：2025-03-04

申请号：US17504755

申请日：2021-10-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sooyoung Park ,  Seunghyun Song ,  Byounghak Hong ,  Seungchan Yun

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

Abstract: Integrated circuit devices and methods of forming the same are provided. Integrated circuit devices may include a first channel layer including a first surface, a second channel layer that is spaced apart from the first channel layer in a first direction and includes a second surface, a first gate electrode and a second gate electrode. The first surface and the second surface may be spaced apart from each other in the first direction and may face opposite directions. The first channel layer may be in the first gate electrode, and the first gate electrode may be absent from the first surface of the first channel layer. The second channel layer may be in the second gate electrode, and the second gate electrode may be absent from the second surface of the second channel layer.

公开(公告)号：US12211837B1

公开(公告)日：2025-01-28

申请号：US18615573

申请日：2024-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myunghoon Jung ,  Jaehong Lee ,  Seungchan Yun ,  Kang-ill Seo

IPC: H01L21/00 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Provided is a semiconductor device which may include: a channel structure; a gate structure on the channel structure; and a gate contact structure on the gate structure, the gate contact structure configured to receive a gate input signal, wherein the gate contact structure is a portion of the gate structure itself, and no connection surface, interface or boundary is formed between the gate contact structure and the gate structure.

公开(公告)号：US11935953B2

公开(公告)日：2024-03-19

申请号：US17967950

申请日：2022-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghwan Han ,  Seungchan Yun

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L29/08

CPC classification number: H01L29/785 ,  H01L21/823864 ,  H01L27/0924 ,  H01L27/1211 ,  H01L21/823814 ,  H01L29/0847 ,  H01L2029/7858

Abstract: A semiconductor device includes a substrate including an active region that extends in a first direction; a gate structure that intersects the active region and that extends in a second direction; a source/drain region on the active region on at least one side of the gate structure; a contact plug on the source/drain region on the at least one side of the gate structure; and a contact insulating layer on sidewalls of the contact plug, wherein a lower end of the contact plug is closer to the substrate than a lower end of the source/drain region.

公开(公告)号：US20230411517A1

公开(公告)日：2023-12-21

申请号：US18239677

申请日：2023-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungchan Yun ,  Donghwan Han

IPC: H01L29/78 ,  H01L27/06 ,  H01L27/088 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L21/822 ,  H01L27/12 ,  H01L21/8234

CPC classification number: H01L29/7827 ,  H01L27/0688 ,  H01L27/088 ,  H01L29/66666 ,  H01L21/823412 ,  H01L29/78696 ,  H01L29/42392 ,  H01L21/8221 ,  H01L27/124 ,  H01L29/78642

Abstract: A semiconductor device includes a plurality of channel layers disposed on an active region of a substrate and spaced apart from each other in a first direction, a first gate structure surrounding the plurality of channel layers, first source/drain regions disposed on the active region on both lateral sides of the first gate structure and contacting the plurality of channel layers and spaced apart from each other in a second direction, an element isolation layer disposed on an upper portion of the first gate structure, a semiconductor layer disposed on the element isolation layer and having a vertical region extending in the first direction and including second source/drain regions spaced apart from each other in the first direction, and a second gate structure disposed to surround a portion of the vertical region. The semiconductor device further includes first to fourth contact plugs.

公开(公告)号：US20230378164A1

公开(公告)日：2023-11-23

申请号：US18366010

申请日：2023-08-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghak Hong ,  Seungchan Yun ,  Kang-ill Seo

IPC: H01L27/02 ,  H01L27/07 ,  H01L29/861 ,  H01L29/739 ,  H01L21/8238

CPC classification number: H01L27/0255 ,  H01L27/0727 ,  H01L29/861 ,  H01L29/7391 ,  H01L21/823807 ,  H01L21/823885

Abstract: Diode structures of stacked devices and methods of forming the same are provided. Diode structures may include a substrate, an upper semiconductor layer that is spaced apart from the substrate in a vertical direction, an upper thin semiconductor layer protruding from a side surface of the upper semiconductor layer in a first horizontal direction, a lower semiconductor layer that is between the substrate and the upper semiconductor layer and has a first conductivity type, a lower thin semiconductor layer protruding from a side surface of the lower semiconductor layer in the first horizontal direction, a first diode contact that is electrically connected to the lower semiconductor layer, and a second diode contact that is electrically connected to one of the upper semiconductor layer and a portion of the substrate. The one of the upper semiconductor layer and the portion of the substrate may have a second conductivity type.

公开(公告)号：US11764207B2

公开(公告)日：2023-09-19

申请号：US17554171

申请日：2021-12-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghak Hong ,  Seungchan Yun ,  Kang-ill Seo

IPC: H01L27/02 ,  H01L27/07 ,  H01L29/861 ,  H01L21/8238 ,  H01L29/739

CPC classification number: H01L27/0255 ,  H01L21/823807 ,  H01L21/823885 ,  H01L27/0727 ,  H01L29/7391 ,  H01L29/861

Abstract: Diode structures of stacked devices and methods of forming the same are provided. Diode structures may include a substrate, an upper semiconductor layer that is spaced apart from the substrate in a vertical direction, an upper thin semiconductor layer protruding from a side surface of the upper semiconductor layer in a first horizontal direction, a lower semiconductor layer that is between the substrate and the upper semiconductor layer and has a first conductivity type, a lower thin semiconductor layer protruding from a side surface of the lower semiconductor layer in the first horizontal direction, a first diode contact that is electrically connected to the lower semiconductor layer, and a second diode contact that is electrically connected to one of the upper semiconductor layer and a portion of the substrate. The one of the upper semiconductor layer and the portion of the substrate may have a second conductivity type.

公开(公告)号：US20230086084A1

公开(公告)日：2023-03-23

申请号：US17554483

申请日：2021-12-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungchan Yun ,  Inchan Hwang ,  Gunho Jo ,  Jeonghyuk Yim ,  Byounghak Hong ,  Kang-ill Seo ,  Ming He ,  JaeHyun Park ,  Mehdi Saremi ,  Rebecca Park ,  Harsono Simka ,  Daewon Ha

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L27/088 ,  H01L29/417 ,  H01L21/8234

Abstract: Transistor devices are provided. A transistor device includes a substrate. The transistor device includes a lower transistor having a lower gate and a lower channel region on the substrate. The transistor device includes an upper transistor having an upper gate and an upper channel region. The lower transistor is between the upper transistor and the substrate. The transistor device includes an isolation region that separates the lower channel region of the lower transistor from the upper channel region of the upper transistor. Moreover, the lower gate of the lower transistor contacts the upper gate of the upper transistor. Related methods of forming a transistor device are also provided.

公开(公告)号：US20250159928A1

公开(公告)日：2025-05-15

申请号：US18732713

申请日：2024-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungchan Yun ,  Kang-Ill Seo

IPC: H01L29/417 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Stacked field-effect transistor (FET) devices are provided. A stacked FET device includes a lower FET having a lower gate structure. The stacked FET device includes a contact that is electrically connected to the lower FET. The stacked FET device includes an upper FET that is on top of the lower FET. The upper FET includes an upper gate structure that includes a conductive gate and an isolation region that is in the conductive gate and on a sidewall of the contact. Moreover, the stacked FET device includes an insulating layer that is between a lower surface of the isolation region and an upper surface of the lower gate structure. Related methods of forming stacked FET devices are also provided.