公开(公告)号：US10177164B2

公开(公告)日：2019-01-08

申请号：US15832756

申请日：2017-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunghan Cho ,  Shinhwan Kang

IPC: H01L27/115 ,  H01L27/11565 ,  H01L23/532 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11582 ,  H01L23/522 ,  H01L29/08

Abstract: A stack structure including a plurality of gate electrodes is vertically stacked on a substrate and extends in a first direction. A channel structure includes vertical channels penetrating the stack structure and a horizontal channel connecting the vertical channels. The horizontal channel are provided under the stack structure. First lower wiring patterns are disposed between the substrate and the stack structure and electrically connected to the channel structure. Each first lower wiring pattern includes a first portion and a second portion having different widths from each other in the first direction.

公开(公告)号：US09847346B2

公开(公告)日：2017-12-19

申请号：US15259941

申请日：2016-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhyun Lee ,  Heonkyu Lee ,  Shinhwan Kang ,  Youngwoo Park

IPC: H01L29/49 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11519

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565

Abstract: A three-dimensional semiconductor memory device includes a stack on a substrate including electrodes vertically stacked on a substrate, lower insulating patterns disposed between the stack and the substrate, the lower insulating patterns being adjacent to both sidewalls of the stack and being spaced apart from each other, a plurality of vertical structures penetrating the stack and being connected to the substrate, and a data storing pattern between the stack and the vertical structures, the data storing pattern including a portion disposed between the lowermost one of the electrodes and the substrate.

公开(公告)号：US12058866B2

公开(公告)日：2024-08-06

申请号：US17204248

申请日：2021-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeryong Sim ,  Shinhwan Kang ,  Jeehoon Han

IPC: H01L29/76 ,  H01L23/48 ,  H01L29/94 ,  H01L31/062 ,  H10B43/27 ,  H10B43/50

CPC classification number: H10B43/50 ,  H01L23/481 ,  H10B43/27

Abstract: A semiconductor device includes a lower structure including a peripheral circuit, a lower insulating structure covering the peripheral circuit, and a pattern structure on the lower insulating structure; a stack structure including interlayer insulating layers and horizontal layers alternately stacked on the lower structure, wherein the horizontal layers include gate horizontal layers in a gate region of the stack structure and first insulating horizontal layers in a first insulating region of the stack structure; a memory vertical structure including a portion penetrating the gate horizontal layers; dummy vertical structures including a portion penetrating the gate horizontal layers; a first peripheral contact plug including a portion penetrating the first insulating region; and gate contact plugs on gate pads of the gate horizontal layers, wherein upper surface of the gate contact plugs and the first peripheral contact plugs are coplanar with each other, wherein the memory vertical structure and the dummy vertical structure are contacting the pattern structure, and wherein at least one of the dummy vertical structures extend further into the pattern structure than the memory vertical structure in a downward direction.

公开(公告)号：US11925020B2

公开(公告)日：2024-03-05

申请号：US17473006

申请日：2021-09-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhwan Kang ,  Younghwan Son ,  Haemin Lee ,  Kohji Kanamori ,  Jeehoon Han

IPC: H10B43/00 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/35

Abstract: A vertical semiconductor device may include a stacked structure and a plurality of channel structures. The stacked structure may include insulation layers and gate patterns alternately and repeatedly stacked on a substrate. The stacked structure may extend in a first direction parallel to an upper surface of the substrate. The gate patterns may include at least ones of first gate patterns. The stacked structure may include a sacrificial pattern between the first gate patterns. The channel structures may pass through the stacked structure. Each of the channel structures may extend to the upper surface of the substrate, and each of the channel structures may include a charge storage structure and a channel. Ones of the channel structures may pass through the sacrificial pattern in the stacked structure to the upper surface of the substrate, and may extend to the upper surface of the substrate.

公开(公告)号：US11716851B2

公开(公告)日：2023-08-01

申请号：US17400224

申请日：2021-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kohji Kanamori ,  Seogoo Kang ,  Shinhwan Kang

IPC: H10B43/27 ,  H01L29/417

CPC classification number: H10B43/27 ,  H01L29/41741

Abstract: A semiconductor memory device including a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer between the first and second semiconductor layers, gate electrodes arranged on the second semiconductor layer and spaced apart from each other in a first direction perpendicular to an upper surface of the second semiconductor layer, and channel structures penetrating the first, second and third semiconductor layers and the gate electrodes, each respective channel structure of channel structures including a gate insulating film, a channel layer, and a buried insulating film, the gate insulating film including a tunnel insulating film adjacent to the channel layer, a charge blocking film adjacent to the gate electrodes, and a charge storage film between the tunnel insulating film and the charge blocking film, and the charge storage film including an upper cover protruding toward the outside of the respective channel structure.

公开(公告)号：US10332902B2

公开(公告)日：2019-06-25

申请号：US15805513

申请日：2017-11-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yunghwan Son ,  Jaesung Sim ,  Shinhwan Kang ,  Youngwoo Park ,  Jaeduk Lee

IPC: H01L27/11575 ,  H01L27/11582 ,  H01L27/11573 ,  H01L29/34 ,  H01L27/11526 ,  G11C5/02 ,  G11C16/04 ,  H01L27/11517 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11548 ,  H01L27/11556 ,  G11C16/30 ,  H01L27/11551

Abstract: A three-dimensional (3D) semiconductor memory device that includes a peripheral logic structure including peripheral logic circuits disposed on a semiconductor substrate and a first insulation layer overlapping the peripheral logic circuits, and a plurality of memory blocks spaced apart from each other on the peripheral logic structure. At least one of the memory blocks includes a well plate electrode, a semiconductor layer in contact with a first surface of the well plate electrode, a stack structure including a plurality of electrodes vertically stacked on the semiconductor layer, and a plurality of vertical structures penetrating the stack structure and connected to the semiconductor layer.

公开(公告)号：US20240357825A1

公开(公告)日：2024-10-24

申请号：US18760980

申请日：2024-07-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeryong Sim ,  Shinhwan Kang ,  Jeehoon Han

IPC: H10B43/50 ,  H01L23/48 ,  H10B43/27

CPC classification number: H10B43/50 ,  H01L23/481 ,  H10B43/27

Abstract: A semiconductor device includes a lower structure including a peripheral circuit, a lower insulating structure covering the peripheral circuit, and a pattern structure on the lower insulating structure; a stack structure including interlayer insulating layers and horizontal layers alternately stacked on the lower structure, wherein the horizontal layers include gate horizontal layers in a gate region of the stack structure and first insulating horizontal layers in a first insulating region of the stack structure; a memory vertical structure including a portion penetrating the gate horizontal layers; dummy vertical structures including a portion penetrating the gate horizontal layers; a first peripheral contact plug including a portion penetrating the first insulating region; and gate contact plugs on gate pads of the gate horizontal layers, wherein upper surface of the gate contact plugs and the first peripheral contact plugs are coplanar with each other, wherein the memory vertical structure and the dummy vertical structure are contacting the pattern structure, and wherein at least one of the dummy vertical structures extend further into the pattern structure than the memory vertical structure in a downward direction.

公开(公告)号：US12120882B2

公开(公告)日：2024-10-15

申请号：US17241343

申请日：2021-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghun Chun ,  Shinhwan Kang ,  Jihwan Kim ,  Jeehoon Han

IPC: H10B43/40 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/40 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A semiconductor device includes a lower structure including a peripheral circuit; a stack structure on the lower structure, extending from a memory cell array region to a stepped region, and including a gate stacked region, and an insulator stacked regions arranged in the stepped region in a first direction; a capping insulating structure on the stack structure; and separation structures passing through the gate stacked region. The stack structure includes interlayer insulating layers and horizontal layers, alternately and repeatedly stacked, the horizontal layers include gate horizontal layers and insulating horizontal layers, the gate stacked region includes the gate horizontal layers, each of the insulator stacked regions includes the insulating horizontal layers, in the stepped region, the stack structure includes a first stepped region, a connection stepped region, and a second stepped region.

公开(公告)号：US12096637B2

公开(公告)日：2024-09-17

申请号：US17352862

申请日：2021-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kohji Kanamori ,  Shinhwan Kang ,  Jeehoon Han

IPC: H10B43/50 ,  H10B41/10 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/50 ,  H10B41/10 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor device includes a substrate; a stack structure on the substrate and including an alternating stack of interlayer insulating layers and gate electrodes; first and second separation regions each extending through the stack structure and extending in a first direction; a first upper separation region between the first and second separation regions and extending through a portion of the stack structure; a plurality of channel structures between the first and second separation regions and extending through the stack structure; and a plurality of first vertical structures each extending through a particular one of the first and second separation regions. Each of the first and second separation regions has a first width in a second direction that is perpendicular to the first direction. Each first vertical structure has a second width in the second direction, the second width being greater than the first width.

公开(公告)号：US11411078B2

公开(公告)日：2022-08-09

申请号：US16701427

申请日：2019-12-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyojoon Ryu ,  Kiyoon Kang ,  Seogoo Kang ,  Shinhwan Kang ,  Jesuk Moon ,  Byunggon Park ,  Jaeryong Sim ,  Jinsoo Lim ,  Jisung Cheon ,  Jeehoon Han

IPC: H01L27/11565 ,  H01L27/11582 ,  H01L29/06 ,  H01L23/31 ,  G11C5/06 ,  H01L27/1157 ,  H01L27/11573

Abstract: A semiconductor device including a substrate having a cell, peripheral, and boundary area; a stack structure on the cell area and including insulating and interconnection layers that are alternately stacked; a molding layer on the peripheral area boundary areas; a selection line isolation pattern extending into the stack structure; a cell channel structure passing through the stack structure; and first dummy patterns extending into the molding layer on the peripheral area, wherein upper surfaces of the first dummy patterns, an upper surface of the selection line isolation pattern, and an upper surface of the cell channel structure are coplanar, and at least one of the first dummy patterns extends in parallel with the selection line isolation pattern or cell channel structure from upper surfaces of the first dummy patterns, the upper surface of the selection line isolation pattern, and the upper surface of the cell channel structure toward the substrate.