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公开(公告)号：US09899097B2
公开(公告)日：2018-02-20
申请号：US15381724
申请日：2016-12-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngmin Kim , Il Han Park , Sung-Won Yun , Hyejin Yim
CPC classification number: G11C16/3459 , G11C11/5671 , G11C16/08 , G11C16/10 , G11C16/3481 , G11C2211/562 , G11C2211/5621 , G11C2211/5644
Abstract: A nonvolatile memory device is provided as follows. A memory cell array includes a plurality of memory cells. An address decoder provides a first verify voltage to selected memory cells among the plurality of memory cells in a first program loop and provides a second verify voltage to the selected memory cells in a second program loop. A control logic determines the second program loop as a verify voltage offset point in which the first verify voltage is changed to the second verify voltage based on a result of a verify operation of the first program loop.
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公开(公告)号：US12165721B2
公开(公告)日：2024-12-10
申请号：US18088046
申请日：2022-12-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kwangho Choi , Jin-Young Kim , Se Hwan Park , Il Han Park , Ji-Sang Lee , Joonsuc Jang
IPC: G11C16/34 , G11C11/56 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/24 , H01L23/00 , H01L25/065 , H01L25/18
Abstract: A nonvolatile memory device includes a memory cell array having cell strings that each includes memory cells stacked on a substrate in a direction perpendicular to the substrate. A row decoder is connected with the memory cells through word lines. The row decoder applies a setting voltage to at least one word line of the word lines and floats the at least one word line during a floating time. A page buffer circuit is connected with the cell strings through bit lines. The page buffer senses voltage changes of the bit lines after the at least one word line is floated during the floating time and outputs a page buffer signal as a sensing result. A counter counts a number of off-cells in response to the page buffer signal. A detecting circuit outputs a detection signal associated with a defect cell based on the number of off-cells.
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公开(公告)号：US11574692B2
公开(公告)日：2023-02-07
申请号：US17359688
申请日：2021-06-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kwangho Choi , Jin-Young Kim , Se Hwan Park , Il Han Park , Ji-Sang Lee , Joonsuc Jang
IPC: G11C16/34 , G11C11/56 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/24 , H01L25/065 , H01L25/18 , H01L23/00
Abstract: A nonvolatile memory device includes a memory cell array having cell strings that each includes memory cells stacked on a substrate in a direction perpendicular to the substrate. A row decoder is connected with the memory cells through word lines. The row decoder applies a setting voltage to at least one word line of the word lines and floats the at least one word line during a floating time. A page buffer circuit is connected with the cell strings through bit lines. The page buffer senses voltage changes of the bit lines after the at least one word line is floated during the floating time and outputs a page buffer signal as a sensing result. A counter counts a number of off-cells in response to the page buffer signal. A detecting circuit outputs a detection signal associated with a defect cell based on the number of off-cells.
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公开(公告)号：US10482973B2
公开(公告)日：2019-11-19
申请号：US16014222
申请日：2018-06-21
Applicant: Samsung Electronics Co. Ltd.
Inventor： Jae-Yun Lee , Joon Soo Kwon , Byung Soo Kim , Sang-Soo Park , Il Han Park , Jong-Hoon Lee
IPC: G11C16/12 , H03K5/135 , G11C16/16 , G11C16/32 , G11C8/08 , G11C16/08 , H03K3/011 , G11C16/30 , G11C5/14 , G11C7/22 , G11C16/04
Abstract: A memory device can include: a memory cell array including a memory cell and a word line that is connected to the memory cell; a clock generator configured to generate a first pumping clock signal from a system clock signal; a charge pump configured to provide a pumping voltage signal using a power supply voltage and the first pumping clock signal; a compensation circuit configured to compensate for variations in a first reference clock signal in accordance with variations in the power supply voltage, and provide a compensated first reference clock signal; and a pass/fail (P/F) determining circuit configured to determine whether the word line is defective by comparing the first pumping clock signal and the compensated first reference clock signal while the pumping voltage signal is provided to the word line.
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15.发明授权公开(公告)号：US09966132B2
公开(公告)日：2018-05-08
申请号：US15478679
申请日：2017-04-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hye Jin Yim , Il Han Park , Hyun Kook Park , Sung Won Yun
CPC classification number: G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/3459 , G11C2211/5648
Abstract: A method for programming a non-volatile memory device includes programming a lower bit in a memory cell included in the non-volatile memory device, reading the lower bit programmed in the memory cell before programming an upper bit in the memory cell, determining a threshold voltage of the memory cell according to a result of reading the lower bit, determining a type of the memory cell using the threshold voltage, and supplying one of a plurality of pulses to a bit line connected to the memory cell according to the determined type of the memory cell.
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Patent Agency Ranking
公开(公告)号：US09947414B2
公开(公告)日：2018-04-17
申请号：US15377504
申请日：2016-12-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jung-Ho Song , Minsu Kim , Il Han Park , Su Chang Jeon
CPC classification number: G11C16/24 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/32 , G11C16/3459 , G11C2207/005
Abstract: An operating method of a nonvolatile memory device is provided. The nonvolatile memory device includes first and second page buffers, and first and second bit lines connected thereto, respectively. First and second latch nodes of the first page buffer are charged to have a voltage having a first level according to data stored in a first latch of the first page buffer. After the charging of the first latch node is started, a sensing node of the second page buffer is pre-charged. The sensing node is connected to the second bit line. Data stored in the first latch is dumped into a second latch of the first page buffer during the pre-charging of the sensing node of the second page buffer.
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公开(公告)号：US09019773B2
公开(公告)日：2015-04-28
申请号：US14037582
申请日：2013-09-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Il Han Park , Seung-Bum Kim
CPC classification number: G11C16/3445 , G11C11/5635 , G11C16/0483 , G11C16/3436 , G11C16/344
Abstract: A nonvolatile memory device includes a memory cell array and control logic. The memory cell array includes multiple memory blocks, each memory block including memory cells connected to word lines and bit lines. The control logic is configured to perform an erase operation in which an erase voltage is applied to a memory block of the multiple memory blocks to erase the memory cells of the memory block, and in which an erase verification voltage is applied a selected word line of the memory block to verify respective erase states of memory cells connected to the selected word line. The control logic is further configured to apply a read voltage to the selected word line to extract erase state information of the memory cells, and to control a level of the erase verification voltage based on the erase state information.
Abstract translation: 非易失性存储器件包括存储单元阵列和控制逻辑。 存储单元阵列包括多个存储块，每个存储块包括连接到字线和位线的存储器单元。 控制逻辑被配置为执行擦除操作，其中擦除电压被施加到多个存储块的存储块以擦除存储块的存储单元，并且其中擦除验证电压被施加到所选择的字线 所述存储块用于验证连接到所选字线的存储单元的相应擦除状态。 控制逻辑还被配置为向所选字线施加读取电压以提取存储器单元的擦除状态信息，并且基于擦除状态信息来控制擦除验证电压的电平。
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公开(公告)号：US20130223156A1
公开(公告)日：2013-08-29
申请号：US13721892
申请日：2012-12-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： NamHee Lee , Kwangil Park , Il Han Park , Sunghwan Seo , Kihwan Choi
CPC classification number: G11C16/3459 , G11C11/5628 , G11C16/10 , G11C2211/5621
Abstract: A program method is provided for a nonvolatile memory device, including a substrate and multiple memory cells formed in a pocket well in the substrate. The program method includes supplying a program voltage to a selected word line during a program execution period of a program loop, supplying a verification voltage to the selected word line during a verification period of the program loop, and supplying a negative voltage to the pocket well as a well bias voltage during the verification period.
Abstract translation: 提供了一种用于非易失性存储器件的编程方法，包括衬底和形成在衬底中的口袋中的多个存储单元。 程序方法包括在程序循环的程序执行期间向所选字线提供编程电压，在程序循环的验证周期期间向所选择的字线提供验证电压，并向口袋提供负电压 作为验证期间的良好偏置电压。
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公开(公告)号：US12073884B2
公开(公告)日：2024-08-27
申请号：US17810067
申请日：2022-06-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Won Jong Song , Doo Hyun Kim , Soon Young Kim , Il Han Park
CPC classification number: G11C16/10 , G06F3/0679 , G11C16/0483
Abstract: A storage device includes a storage controller that receives a protecting command before a thermal process is performed in the storage device, and that generates a protecting pattern by programming a protecting voltage in a converged region where threshold voltage distributions of memory cells in the storage device converge after the thermal process is performed on the storage device.
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20.发明授权公开(公告)号：US12040020B2
公开(公告)日：2024-07-16
申请号：US17854163
申请日：2022-06-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kwangho Choi , Minseok Kim , Il Han Park , Jun-Yong Park , Joonsuc Jang
CPC classification number: G11C16/0433 , G11C16/08 , G11C16/12 , G11C16/26
Abstract: Disclosed is a memory device which includes a history table and communicates with a storage controller. A method of operating the memory device includes receiving a first request indicating a first core operation of a first memory block from the storage controller, determining whether history data of the first memory block have a first value or a second value, with reference to the history table, in response to the first request, when it is determined that the history data of the first memory block have the first value, performing the first core operation corresponding to a first type on the first memory block, and after performing the first core operation corresponding to the first type on the first memory block, updating the history data of the first memory block in the history table from the first value to the second value.
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